[PATCH] Add AMD znver6 processor support
Jan Beulich
jbeulich@suse.com
Fri Nov 14 14:46:58 GMT 2025
On 14.11.2025 15:24, Kalvakuntla, Umesh wrote:
> Thank you Jan Beulich, Haochen Jiang, Christian Ludloff for the review.
>
> I've addressed all the review comments.
> Regarding the prereq for AVX512_BMM, I've added as suggested AVX512BW & AVX512VL.
Are you sure about the AVX512VL part? I.e. do the new insns really not act like
all others wrt that sub-feature?
I'll take a closer look next week. For the future, however, please submit new
patch versions as new threads, properly tagged with the version, rather than as
reply to an earlier thread.
Jan
> Also added documentation as part of commit log.
>
>
> Thank you,
> Umesh
>
> commit 90c2eadf42c971238017b5fdbdbd4003f67c3567
> Author: Umesh Kalvakuntla <umesh.kalvakuntla@amd.com>
> Date: Fri Nov 14 19:27:21 2025 +0530
>
> Add AMD znver6 processor support
>
> Please find the ISA descriptions for AVX512_BMM instructions below.
>
> AVX512 Bit Manipulation Instructions
> ====================================
> The AVX512BMM instructions include Bit Matrix Multiply and Bit Reversal
> operations.
>
> CPUID
> -----
> Support is indicated by the new CPUID 8000_0021, EAX bit 23, labeled AVX512_BMM.
>
> Encoding
> --------
> VBMACOR16x16x16
> EVEX.256.NP.MAP6.W0 80 /r VBMACOR16x16x16 ymm1, ymm2, ymm3/m256
> EVEX.512.NP.MAP6.W0 80 /r VBMACOR16x16x16 zmm1, zmm2, zmm3/m512
>
> VBMACXOR16x16x16
> EVEX.256.NP.MAP6.W1 80 /r VBMACXOR16x16x16 ymm1, ymm2, ymm3/m256
> EVEX.512.NP.MAP6.W1 80 /r VBMACXOR16x16x16 zmm1, zmm2, zmm3/m512
>
> DESCRIPTION
> -----------
> 256 BIT VERSIONS
> ----------------
> 16x16 non-transposed fused BMM-accumulate (BMAC) with OR/XOR reduction.
> A ymm register holds a 16x16 bit matrix. The third source matrix for
> accumulation is in ymm1.
>
> 512 BIT VERSIONS
> ----------------
> 2 parallel 16x16 non-transposed fused BMM-accumulate (BMAC) with OR/XOR
> reduction.
> Each 256-bit chunk of a zmm register holds a 16x16 bit matrix. The third source
> matrices for accumulation are in zmm1.
>
> VBITREV
> -------
> EVEX.128.NP.MAP6.W0 81 /r VBITREV xmm1{k1}{z}, xmm2/m128
> EVEX.256.NP.MAP6.W0 81 /r VBITREV ymm1{k1}{z}, ymm2/m256
> EVEX.512.NP.MAP6.W0 81 /r VBITREV zmm1{k1}{z}, zmm2/m512
>
> DESCRIPTION
> -----------
> Bit reversal within a byte boundary. Only applied to input bytes where the
> corresponding mask bit is set; otherwise, bytes are left untouched or zeroed out
> if zero masking is indicated.
>
> gas/ChangeLog:
>
> * NEWS: Add AMD Zen6 ARCH.
> * config/tc-i386.c: Add znver6 ARCH, avx512_bmm SUBARCH.
> * doc/c-i386.texi: Likewise.
> * testsuite/gas/i386/i386.exp: Add znver6 test cases.
> * testsuite/gas/i386/x86-64.exp: Add znver6 test cases.
> * testsuite/gas/i386/arch-16-znver6.d: New test.
> * testsuite/gas/i386/arch-16.d: New test.
> * testsuite/gas/i386/arch-16.s: New test.
> * testsuite/gas/i386/avx512_bmm-inval.l: New test.
> * testsuite/gas/i386/avx512_bmm-inval.s: New test.
> * testsuite/gas/i386/avx512_bmm.d: New test.
> * testsuite/gas/i386/avx512_bmm.s: New test.
> * testsuite/gas/i386/x86-64-arch-6-znver6.d: New test.
> * testsuite/gas/i386/x86-64-arch-6.d: New test.
> * testsuite/gas/i386/x86-64-arch-6.s: New test.
> * testsuite/gas/i386/x86-64-avx512_bmm-inval.l: New test.
> * testsuite/gas/i386/x86-64-avx512_bmm-inval.s: New test.
> * testsuite/gas/i386/x86-64-avx512_bmm.d: New test.
> * testsuite/gas/i386/x86-64-avx512_bmm.s: New test.
>
> opcodes/ChangeLog:
>
> * i386-dis-evex-w.h: Likewise.
> * i386-dis-evex.h: Likewise.
> * i386-dis.c: Add EVEX_W_MAP6_80, EVEX_W_MAP6_81.
> * i386-gen.c: Likewise.
> * i386-init.h: Re-generated.
> * i386-mnem.h: Re-generated.
> * i386-opc.h (enum i386_cpu): Add CpuAVX512_BMM.
> (i386_cpu_flags): Add cpuvavx512_bmm.
> * i386-opc.tbl: Add vbmacor16x16x16, vbmacxor16x16x16, vbitrev.
> * i386-tbl.h: Re-generated.
>
> diff --git a/gas/NEWS b/gas/NEWS
> index 4bd3d747aa5..4a79c999983 100644
> --- a/gas/NEWS
> +++ b/gas/NEWS
> @@ -1,5 +1,7 @@
> -*- text -*-
>
> +* Add support for AMD Zen6 processor.
> +
> * Emit an SFrame FRE with zero offsets to convey an undefined return address
> in the SFrame stack trace format.
>
> diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
> index eb282bff43c..d219da8c2c1 100644
> --- a/gas/config/tc-i386.c
> +++ b/gas/config/tc-i386.c
> @@ -1091,6 +1091,7 @@ static const arch_entry cpu_arch[] =
> ARCH (znver3, ZNVER, ZNVER3, false),
> ARCH (znver4, ZNVER, ZNVER4, false),
> ARCH (znver5, ZNVER, ZNVER5, false),
> + ARCH (znver6, ZNVER, ZNVER6, false),
> ARCH (btver1, BT, BTVER1, false),
> ARCH (btver2, BT, BTVER2, false),
>
> @@ -1208,6 +1209,7 @@ static const arch_entry cpu_arch[] =
> VECARCH (avx512_bf16, AVX512_BF16, ANY_AVX512_BF16, reset),
> VECARCH (avx512_vp2intersect, AVX512_VP2INTERSECT,
> ANY_AVX512_VP2INTERSECT, reset),
> + VECARCH (avx512_bmm, AVX512_BMM, ANY_AVX512_BMM, reset),
> SUBARCH (tdx, TDX, TDX, false),
> SUBARCH (enqcmd, ENQCMD, ENQCMD, false),
> SUBARCH (serialize, SERIALIZE, SERIALIZE, false),
> diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
> index b03ac64a78a..f02e064df20 100644
> --- a/gas/doc/c-i386.texi
> +++ b/gas/doc/c-i386.texi
> @@ -126,6 +126,7 @@ processor names are recognized:
> @code{znver3},
> @code{znver4},
> @code{znver5},
> +@code{znver6},
> @code{btver1},
> @code{btver2},
> @code{generic32} and
> @@ -198,6 +199,7 @@ accept various extension mnemonics. For example,
> @code{avx512_bf16},
> @code{avx_vnni},
> @code{avx512_fp16},
> +@code{avx512_bmm},
> @code{prefetchi},
> @code{avx_ifma},
> @code{avx_vnni_int8},
> @@ -1691,9 +1693,9 @@ supported on the CPU specified. The choices for @var{cpu_type} are:
> @item @samp{k6} @tab @samp{k6_2} @tab @samp{athlon} @tab @samp{k8}
> @item @samp{amdfam10} @tab @samp{bdver1} @tab @samp{bdver2} @tab @samp{bdver3}
> @item @samp{bdver4} @tab @samp{znver1} @tab @samp{znver2} @tab @samp{znver3}
> -@item @samp{znver4} @tab @samp{znver5} @tab @samp{btver1} @tab @samp{btver2}
> -@item @samp{generic32}
> -@item @samp{generic64} @tab @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
> +@item @samp{znver4} @tab @samp{znver5} @tab @samp{znver6} @tab @samp{btver1}
> +@item @samp{btver2} @tab @samp{generic32} @tab @samp{generic64}
> +@item @samp{.cmov} @tab @samp{.fxsr} @tab @samp{.mmx}
> @item @samp{.sse} @tab @samp{.sse2} @tab @samp{.sse3} @tab @samp{.sse4a}
> @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
> @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.ept}
> diff --git a/gas/testsuite/gas/i386/arch-16-znver6.d b/gas/testsuite/gas/i386/arch-16-znver6.d
> new file mode 100644
> index 00000000000..2930de0a7c3
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/arch-16-znver6.d
> @@ -0,0 +1,15 @@
> +#source: arch-16.s
> +#as: -march=znver6
> +#objdump: -dw
> +#name: i386 arch 16 (znver6)
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +[0-9a-f]+ <\.text>:
> +[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1
> +[\s]*[a-f0-9]+:[\s]*c4 e2 f1 b5 d1[\s]*\{vex\} vpmadd52huq %xmm1,%xmm1,%xmm2
> +[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3
> diff --git a/gas/testsuite/gas/i386/arch-16.d b/gas/testsuite/gas/i386/arch-16.d
> new file mode 100644
> index 00000000000..6c6e500b671
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/arch-16.d
> @@ -0,0 +1,13 @@
> +#objdump: -dw
> +#name: i386 arch 6
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +[0-9a-f]+ <\.text>:
> +[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1
> +[\s]*[a-f0-9]+:[\s]*62 f2 f5 08 b5 d1[\s]*vpmadd52huq %xmm1,%xmm1,%xmm2
> +[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3
> \ No newline at end of file
> diff --git a/gas/testsuite/gas/i386/arch-16.s b/gas/testsuite/gas/i386/arch-16.s
> new file mode 100644
> index 00000000000..58d80b5bc88
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/arch-16.s
> @@ -0,0 +1,8 @@
> +# Test -march=
> + .text
> +
> + vbmacor16x16x16 %ymm1, %ymm2, %ymm3 #AVX512BMM
> + vbcstnebf162ps (%edx), %xmm1 #AVX_NE_CONVERT
> + vpmadd52huq %xmm1, %xmm1, %xmm2 #AVX_IFMA
> + vpdpbssd %ymm1, %ymm2, %ymm3 #AVX_VNNI_INT8
> + vaddph %zmm1, %zmm2, %zmm3 #AVX512-FP16
> diff --git a/gas/testsuite/gas/i386/avx512_bmm-inval.l b/gas/testsuite/gas/i386/avx512_bmm-inval.l
> new file mode 100644
> index 00000000000..2240afe6992
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/avx512_bmm-inval.l
> @@ -0,0 +1,3 @@
> +.* Assembler messages:
> +.*:5: Error: operand .* `vbmacor16x16x16'
> +.*:6: Error: operand .* `vbmacxor16x16x16'
> diff --git a/gas/testsuite/gas/i386/avx512_bmm-inval.s b/gas/testsuite/gas/i386/avx512_bmm-inval.s
> new file mode 100644
> index 00000000000..61922463d31
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/avx512_bmm-inval.s
> @@ -0,0 +1,6 @@
> +# Check illegal 32bit AVX512_BMM instructions
> +
> + .text
> +_start:
> + vbmacor16x16x16 %xmm1, %xmm2, %xmm3
> + vbmacxor16x16x16 %xmm1, %xmm2, %xmm3
> diff --git a/gas/testsuite/gas/i386/avx512_bmm.d b/gas/testsuite/gas/i386/avx512_bmm.d
> new file mode 100644
> index 00000000000..989dfd6c003
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/avx512_bmm.d
> @@ -0,0 +1,42 @@
> +#objdump: -dw
> +#name: i386 AVX512_BMM insns
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +[0-9a-f]+ <bmm>:
> +[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 92 00 10 00 00[\s]*vbmacor16x16x16 0x1000\(%edx\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 74 28 80 52 80[\s]*vbmacor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 6c 48 80 d9[\s]*vbmacor16x16x16 %zmm1,%zmm2,%zmm3
> +[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 92 00 20 00 00[\s]*vbmacor16x16x16 0x2000\(%edx\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 74 48 80 52 80[\s]*vbmacor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 ec 28 80 d9[\s]*vbmacxor16x16x16 %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 92 00 10 00 00[\s]*vbmacxor16x16x16 0x1000\(%edx\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 28 80 52 80[\s]*vbmacxor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 ec 48 80 d9[\s]*vbmacxor16x16x16 %zmm1,%zmm2,%zmm3
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 92 00 20 00 00[\s]*vbmacxor16x16x16 0x2000\(%edx\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 f4 48 80 52 80[\s]*vbmacxor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 d1[\s]*vbitrev %xmm1,%xmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 d1[\s]*vbitrev %xmm1,%xmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 94 f4 c0 1d fe ff[\s]*vbitrev -0x1e240\(%esp,%esi,8\),%xmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 94 f4 c0 1d fe ff[\s]*vbitrev -0x1e240\(%esp,%esi,8\),%xmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 92 00 08 00 00[\s]*vbitrev 0x800\(%edx\),%xmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 52 80[\s]*vbitrev -0x800\(%edx\),%xmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 d1[\s]*vbitrev %ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 d1[\s]*vbitrev %ymm1,%ymm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 94 f4 c0 1d fe ff[\s]*vbitrev -0x1e240\(%esp,%esi,8\),%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 94 f4 c0 1d fe ff[\s]*vbitrev -0x1e240\(%esp,%esi,8\),%ymm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 90 00 10 00 00[\s]*vbitrev 0x1000\(%eax\),%ymm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 50 80[\s]*vbitrev -0x1000\(%eax\),%ymm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 d1[\s]*vbitrev %zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 d1[\s]*vbitrev %zmm1,%zmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 94 f4 c0 1d fe ff[\s]*vbitrev -0x1e240\(%esp,%esi,8\),%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 94 f4 c0 1d fe ff[\s]*vbitrev -0x1e240\(%esp,%esi,8\),%zmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 92 00 20 00 00[\s]*vbitrev 0x2000\(%edx\),%zmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 52 80[\s]*vbitrev -0x2000\(%edx\),%zmm2\{%k1\}\{z\}
> \ No newline at end of file
> diff --git a/gas/testsuite/gas/i386/avx512_bmm.s b/gas/testsuite/gas/i386/avx512_bmm.s
> new file mode 100644
> index 00000000000..8d3d5dcfec5
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/avx512_bmm.s
> @@ -0,0 +1,40 @@
> +# Check 32bit AVX512_BMM instructions
> +
> + .text
> +bmm:
> + vbmacor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM
> + vbmacor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM
> + vbmacor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM
> + vbmacor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM Disp8
> + vbmacor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM
> + vbmacor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM
> + vbmacor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM
> + vbmacor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8
> +
> + vbmacxor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM
> + vbmacxor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM
> + vbmacxor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM
> + vbmacxor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM Disp8
> + vbmacxor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM
> + vbmacxor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM
> + vbmacxor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM
> + vbmacxor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8
> +
> + vbitrev %xmm1, %xmm2 # AVX512_BMM
> + vbitrev %xmm1, %xmm2{%k1}{z} # AVX512_BMM
> + vbitrev -123456(%esp,%esi,8), %xmm2 # AVX512_BMM
> + vbitrev -123456(%esp,%esi,8), %xmm2{%k1}{z} # AVX512_BMM
> + vbitrev 2048(%edx), %xmm2{%k1}{z} # AVX512_BMM
> + vbitrev -2048(%edx), %xmm2{%k1}{z} # AVX512_BMM Disp8
> + vbitrev %ymm1, %ymm2 # AVX512_BMM
> + vbitrev %ymm1, %ymm2{%k1}{z} # AVX512_BMM
> + vbitrev -123456(%esp,%esi,8), %ymm2 # AVX512_BMM
> + vbitrev -123456(%esp,%esi,8), %ymm2{%k1}{z} # AVX512_BMM
> + vbitrev 4096(%eax), %ymm2{%k1}{z} # AVX512_BMM
> + vbitrev -4096(%eax), %ymm2{%k1}{z} # AVX512_BMM Disp8
> + vbitrev %zmm1, %zmm2 # AVX512_BMM
> + vbitrev %zmm1, %zmm2{%k1}{z} # AVX512_BMM
> + vbitrev -123456(%esp,%esi,8), %zmm2 # AVX512_BMM
> + vbitrev -123456(%esp,%esi,8), %zmm2{%k1}{z} # AVX512_BMM
> + vbitrev 8192(%edx), %zmm2{%k1}{z} # AVX512_BMM
> + vbitrev -8192(%edx), %zmm2{%k1}{z} # AVX512_BMM Disp8
> diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
> index 9b23a7b671d..b2c673a7376 100644
> --- a/gas/testsuite/gas/i386/i386.exp
> +++ b/gas/testsuite/gas/i386/i386.exp
> @@ -215,6 +215,7 @@ if [gas_32_check] then {
> run_dump_test "arch-14-znver3"
> run_dump_test "arch-14-znver4"
> run_dump_test "arch-15-znver5"
> + run_dump_test "arch-16-znver6"
> run_dump_test "arch-10-btver1"
> run_dump_test "arch-10-btver2"
> run_list_test "arch-10-1" "-march=generic32 -I${srcdir}/$subdir -al"
> @@ -229,6 +230,7 @@ if [gas_32_check] then {
> run_dump_test "arch-14"
> run_dump_test "arch-14-1"
> run_dump_test "arch-15"
> + run_dump_test "arch-16"
> run_list_test "arch-dflt" "-march=generic32 -al"
> run_list_test "arch-stk" "-march=generic32 -al"
> run_dump_test "8087"
> @@ -479,6 +481,8 @@ if [gas_32_check] then {
> run_dump_test "avx512vnni-intel"
> run_dump_test "avx512vnni_vl"
> run_dump_test "avx512vnni_vl-intel"
> + run_dump_test "avx512_bmm"
> + run_list_test "avx512_bmm-inval"
> run_dump_test "avx512bitalg"
> run_dump_test "avx512bitalg-intel"
> run_dump_test "avx512bitalg_vl"
> diff --git a/gas/testsuite/gas/i386/x86-64-arch-6-znver6.d b/gas/testsuite/gas/i386/x86-64-arch-6-znver6.d
> new file mode 100644
> index 00000000000..e4da11447a0
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-arch-6-znver6.d
> @@ -0,0 +1,15 @@
> +#source: x86-64-arch-6.s
> +#as: -march=znver6
> +#objdump: -dw
> +#name: x86-64 arch 6 (znver6)
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +[0-9a-f]+ <\.text>:
> +[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*67 c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1
> +[\s]*[a-f0-9]+:[\s]*c4 e2 f1 b5 d1[\s]*\{vex\} vpmadd52huq %xmm1,%xmm1,%xmm2
> +[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3
> diff --git a/gas/testsuite/gas/i386/x86-64-arch-6.d b/gas/testsuite/gas/i386/x86-64-arch-6.d
> new file mode 100644
> index 00000000000..5eb83ac8f2f
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-arch-6.d
> @@ -0,0 +1,13 @@
> +#objdump: -dw
> +#name: x86-64 arch 6
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +[0-9a-f]+ <\.text>:
> +[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*67 c4 e2 7a b1 0a[\s]*vbcstnebf162ps \(%edx\),%xmm1
> +[\s]*[a-f0-9]+:[\s]*62 f2 f5 08 b5 d1[\s]*vpmadd52huq %xmm1,%xmm1,%xmm2
> +[\s]*[a-f0-9]+:[\s]*c4 e2 6f 50 d9[\s]*vpdpbssd %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*62 f5 6c 48 58 d9[\s]*vaddph %zmm1,%zmm2,%zmm3
> \ No newline at end of file
> diff --git a/gas/testsuite/gas/i386/x86-64-arch-6.s b/gas/testsuite/gas/i386/x86-64-arch-6.s
> new file mode 100644
> index 00000000000..58d80b5bc88
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-arch-6.s
> @@ -0,0 +1,8 @@
> +# Test -march=
> + .text
> +
> + vbmacor16x16x16 %ymm1, %ymm2, %ymm3 #AVX512BMM
> + vbcstnebf162ps (%edx), %xmm1 #AVX_NE_CONVERT
> + vpmadd52huq %xmm1, %xmm1, %xmm2 #AVX_IFMA
> + vpdpbssd %ymm1, %ymm2, %ymm3 #AVX_VNNI_INT8
> + vaddph %zmm1, %zmm2, %zmm3 #AVX512-FP16
> diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bmm-inval.l b/gas/testsuite/gas/i386/x86-64-avx512_bmm-inval.l
> new file mode 100644
> index 00000000000..2240afe6992
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-avx512_bmm-inval.l
> @@ -0,0 +1,3 @@
> +.* Assembler messages:
> +.*:5: Error: operand .* `vbmacor16x16x16'
> +.*:6: Error: operand .* `vbmacxor16x16x16'
> diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bmm-inval.s b/gas/testsuite/gas/i386/x86-64-avx512_bmm-inval.s
> new file mode 100644
> index 00000000000..eecea2db91c
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-avx512_bmm-inval.s
> @@ -0,0 +1,6 @@
> +# Check illegal 64bit AVX512_BMM instructions
> +
> + .text
> +_start:
> + vbmacor16x16x16 %xmm1, %xmm2, %xmm3
> + vbmacxor16x16x16 %xmm1, %xmm2, %xmm3
> diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bmm.d b/gas/testsuite/gas/i386/x86-64-avx512_bmm.d
> new file mode 100644
> index 00000000000..8026d2be563
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-avx512_bmm.d
> @@ -0,0 +1,42 @@
> +#objdump: -dw
> +#name: x86-64 AVX512_BMM insns
> +
> +.*: +file format .*
> +
> +Disassembly of section \.text:
> +
> +[0-9a-f]+ <bmm>:
> +[\s]*[a-f0-9]+:[\s]*62 f6 6c 28 80 d9[\s]*vbmacor16x16x16 %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 74 28 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 74 28 80 92 00 10 00 00[\s]*vbmacor16x16x16 0x1000\(%edx\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 74 28 80 52 80[\s]*vbmacor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 6c 48 80 d9[\s]*vbmacor16x16x16 %zmm1,%zmm2,%zmm3
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 74 48 80 94 f4 c0 1d fe ff[\s]*vbmacor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 74 48 80 92 00 20 00 00[\s]*vbmacor16x16x16 0x2000\(%edx\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 74 48 80 52 80[\s]*vbmacor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 ec 28 80 d9[\s]*vbmacxor16x16x16 %ymm1,%ymm2,%ymm3
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 28 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 28 80 92 00 10 00 00[\s]*vbmacxor16x16x16 0x1000\(%edx\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 28 80 52 80[\s]*vbmacxor16x16x16 -0x1000\(%edx\),%ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 ec 48 80 d9[\s]*vbmacxor16x16x16 %zmm1,%zmm2,%zmm3
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 48 80 94 f4 c0 1d fe ff[\s]*vbmacxor16x16x16 -0x1e240\(%esp,%esi,8\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 48 80 92 00 20 00 00[\s]*vbmacxor16x16x16 0x2000\(%edx\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 f4 48 80 52 80[\s]*vbmacxor16x16x16 -0x2000\(%edx\),%zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 08 81 d1[\s]*vbitrev %xmm1,%xmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 89 81 d1[\s]*vbitrev %xmm1,%xmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 08 81 94 f4 c0 1d fe ff[\s]*vbitrev -0x1e240\(%esp,%esi,8\),%xmm2
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 89 81 94 f4 c0 1d fe ff[\s]*vbitrev -0x1e240\(%esp,%esi,8\),%xmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 89 81 92 00 08 00 00[\s]*vbitrev 0x800\(%edx\),%xmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 89 81 52 80[\s]*vbitrev -0x800\(%edx\),%xmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 28 81 d1[\s]*vbitrev %ymm1,%ymm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c a9 81 d1[\s]*vbitrev %ymm1,%ymm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 28 81 94 f4 c0 1d fe ff[\s]*vbitrev -0x1e240\(%esp,%esi,8\),%ymm2
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c a9 81 94 f4 c0 1d fe ff[\s]*vbitrev -0x1e240\(%esp,%esi,8\),%ymm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c a9 81 90 00 10 00 00[\s]*vbitrev 0x1000\(%eax\),%ymm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c a9 81 50 80[\s]*vbitrev -0x1000\(%eax\),%ymm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c 48 81 d1[\s]*vbitrev %zmm1,%zmm2
> +[\s]*[a-f0-9]+:[\s]*62 f6 7c c9 81 d1[\s]*vbitrev %zmm1,%zmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c 48 81 94 f4 c0 1d fe ff[\s]*vbitrev -0x1e240\(%esp,%esi,8\),%zmm2
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c c9 81 94 f4 c0 1d fe ff[\s]*vbitrev -0x1e240\(%esp,%esi,8\),%zmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c c9 81 92 00 20 00 00[\s]*vbitrev 0x2000\(%edx\),%zmm2\{%k1\}\{z\}
> +[\s]*[a-f0-9]+:[\s]*67 62 f6 7c c9 81 52 80[\s]*vbitrev -0x2000\(%edx\),%zmm2\{%k1\}\{z\}
> diff --git a/gas/testsuite/gas/i386/x86-64-avx512_bmm.s b/gas/testsuite/gas/i386/x86-64-avx512_bmm.s
> new file mode 100644
> index 00000000000..6a8f1763b95
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-avx512_bmm.s
> @@ -0,0 +1,40 @@
> +# Check 64bit AVX512_BMM instructions
> +
> + .text
> +bmm:
> + vbmacor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM
> + vbmacor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM
> + vbmacor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM
> + vbmacor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM Disp8
> + vbmacor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM
> + vbmacor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM
> + vbmacor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM
> + vbmacor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8
> +
> + vbmacxor16x16x16 %ymm1, %ymm2, %ymm3 # AVX512_BMM
> + vbmacxor16x16x16 -123456(%esp,%esi,8), %ymm1, %ymm2 # AVX512_BMM
> + vbmacxor16x16x16 4096(%edx), %ymm1, %ymm2 # AVX512_BMM
> + vbmacxor16x16x16 -4096(%edx), %ymm1, %ymm2 # AVX512_BMM Disp8
> + vbmacxor16x16x16 %zmm1, %zmm2, %zmm3 # AVX512_BMM
> + vbmacxor16x16x16 -123456(%esp,%esi,8), %zmm1, %zmm2 # AVX512_BMM
> + vbmacxor16x16x16 8192(%edx), %zmm1, %zmm2 # AVX512_BMM
> + vbmacxor16x16x16 -8192(%edx), %zmm1, %zmm2 # AVX512_BMM Disp8
> +
> + vbitrev %xmm1, %xmm2 # AVX512_BMM
> + vbitrev %xmm1, %xmm2{%k1}{z} # AVX512_BMM
> + vbitrev -123456(%esp,%esi,8), %xmm2 # AVX512_BMM
> + vbitrev -123456(%esp,%esi,8), %xmm2{%k1}{z} # AVX512_BMM
> + vbitrev 2048(%edx), %xmm2{%k1}{z} # AVX512_BMM
> + vbitrev -2048(%edx), %xmm2{%k1}{z} # AVX512_BMM Disp8
> + vbitrev %ymm1, %ymm2 # AVX512_BMM
> + vbitrev %ymm1, %ymm2{%k1}{z} # AVX512_BMM
> + vbitrev -123456(%esp,%esi,8), %ymm2 # AVX512_BMM
> + vbitrev -123456(%esp,%esi,8), %ymm2{%k1}{z} # AVX512_BMM
> + vbitrev 4096(%eax), %ymm2{%k1}{z} # AVX512_BMM
> + vbitrev -4096(%eax), %ymm2{%k1}{z} # AVX512_BMM Disp8
> + vbitrev %zmm1, %zmm2 # AVX512_BMM
> + vbitrev %zmm1, %zmm2{%k1}{z} # AVX512_BMM
> + vbitrev -123456(%esp,%esi,8), %zmm2 # AVX512_BMM
> + vbitrev -123456(%esp,%esi,8), %zmm2{%k1}{z} # AVX512_BMM
> + vbitrev 8192(%edx), %zmm2{%k1}{z} # AVX512_BMM
> + vbitrev -8192(%edx), %zmm2{%k1}{z} # AVX512_BMM Disp8
> diff --git a/gas/testsuite/gas/i386/x86-64.exp b/gas/testsuite/gas/i386/x86-64.exp
> index 738cd31b1a0..ab10233e56b 100644
> --- a/gas/testsuite/gas/i386/x86-64.exp
> +++ b/gas/testsuite/gas/i386/x86-64.exp
> @@ -182,6 +182,7 @@ run_dump_test "x86-64-arch-4"
> run_dump_test "x86-64-arch-4-1"
> run_dump_test "rmpquery"
> run_dump_test "x86-64-arch-5"
> +run_dump_test "x86-64-arch-6"
> run_dump_test "x86-64-arch-2-lzcnt"
> run_dump_test "x86-64-arch-2-prefetchw"
> run_dump_test "x86-64-arch-2-bdver1"
> @@ -193,6 +194,7 @@ run_dump_test "x86-64-arch-3-znver2"
> run_dump_test "x86-64-arch-4-znver3"
> run_dump_test "x86-64-arch-4-znver4"
> run_dump_test "x86-64-arch-5-znver5"
> +run_dump_test "x86-64-arch-6-znver6"
> run_dump_test "x86-64-arch-2-btver1"
> run_dump_test "x86-64-arch-2-btver2"
> run_list_test "x86-64-arch-2-1" "-march=generic64 -I${srcdir}/$subdir -al"
> @@ -441,6 +443,8 @@ run_dump_test "x86-64-avx512vnni"
> run_dump_test "x86-64-avx512vnni-intel"
> run_dump_test "x86-64-avx512vnni_vl"
> run_dump_test "x86-64-avx512vnni_vl-intel"
> +run_dump_test "x86-64-avx512_bmm"
> +run_list_test "x86-64-avx512_bmm-inval"
> run_dump_test "x86-64-avx512bitalg"
> run_dump_test "x86-64-avx512bitalg-intel"
> run_dump_test "x86-64-avx512bitalg_vl"
> diff --git a/opcodes/i386-dis-evex-w.h b/opcodes/i386-dis-evex-w.h
> index bfdcfb29fdd..997a61033a3 100644
> --- a/opcodes/i386-dis-evex-w.h
> +++ b/opcodes/i386-dis-evex-w.h
> @@ -524,3 +524,13 @@
> {
> { "vmovw", { EXwS, XMScalar }, 0 },
> },
> + /* EVEX_W_MAP6_80 */
> + {
> + { "vbmacor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
> + { "vbmacxor16x16x16", { XM, Vex, EXx }, NO_PREFIX },
> + },
> + /* EVEX_W_MAP6_81 */
> + {
> + { "vbitrev", { XM, EXx }, NO_PREFIX },
> + { Bad_Opcode }
> + }
> diff --git a/opcodes/i386-dis-evex.h b/opcodes/i386-dis-evex.h
> index 3c24c224efc..b2f02e494f9 100644
> --- a/opcodes/i386-dis-evex.h
> +++ b/opcodes/i386-dis-evex.h
> @@ -1601,8 +1601,8 @@ static const struct dis386 evex_table[][256] = {
> { Bad_Opcode },
> { Bad_Opcode },
> /* 80 */
> - { Bad_Opcode },
> - { Bad_Opcode },
> + { VEX_W_TABLE (EVEX_W_MAP6_80) },
> + { VEX_W_TABLE (EVEX_W_MAP6_81) },
> { Bad_Opcode },
> { Bad_Opcode },
> { Bad_Opcode },
> diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
> index ac37a96957b..bb2294abb07 100644
> --- a/opcodes/i386-dis.c
> +++ b/opcodes/i386-dis.c
> @@ -1855,6 +1855,8 @@ enum
> EVEX_W_MAP5_6E_P_1,
> EVEX_W_MAP5_7A_P_3,
> EVEX_W_MAP5_7E_P_1,
> + EVEX_W_MAP6_80,
> + EVEX_W_MAP6_81,
> };
>
> typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
> diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
> index bc86f2befbb..dbea02f1a9f 100644
> --- a/opcodes/i386-gen.c
> +++ b/opcodes/i386-gen.c
> @@ -98,6 +98,8 @@ static const dependency isa_dependencies[] =
> "ZNVER3|AVX512F|AVX512DQ|AVX512IFMA|AVX512CD|AVX512BW|AVX512VL|AVX512_BF16|AVX512VBMI|AVX512_VBMI2|AVX512_VNNI|AVX512_BITALG|AVX512_VPOPCNTDQ|GFNI|RMPQUERY" },
> { "ZNVER5",
> "ZNVER4|AVX_VNNI|MOVDIRI|MOVDIR64B|AVX512_VP2INTERSECT|PREFETCHI" },
> + { "ZNVER6",
> + "ZNVER5|AVX512_BMM|AVX_NE_CONVERT|AVX_IFMA|AVX_VNNI_INT8|AVX512_FP16" },
> { "BTVER1",
> "GENERIC64|FISTTP|MONITOR|CX16|LAHF_SAHF|Rdtscp|SSSE3|SSE4A|ABM|PRFCHW|Clflush|FISTTP|SVME" },
> { "BTVER2",
> @@ -208,6 +210,8 @@ static const dependency isa_dependencies[] =
> "AVX512BW" },
> { "AVX512_VP2INTERSECT",
> "AVX512F" },
> + { "AVX512_BMM",
> + "AVX512VL|AVX512BW" },
> { "AVX512_BF16",
> "AVX512BW" },
> { "AVX512_FP16",
> @@ -417,6 +421,7 @@ static bitfield cpu_flags[] =
> BITFIELD (AVX512_BITALG),
> BITFIELD (AVX512_BF16),
> BITFIELD (AVX512_VP2INTERSECT),
> + BITFIELD (AVX512_BMM),
> BITFIELD (TDX),
> BITFIELD (AVX_VNNI),
> BITFIELD (AVX512_FP16),
> diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
> index 29e7d0cac9b..1f4561d148f 100644
> --- a/opcodes/i386-opc.h
> +++ b/opcodes/i386-opc.h
> @@ -205,6 +205,8 @@ enum i386_cpu
> CpuAVX512_BF16,
> /* Intel AVX-512 VP2INTERSECT Instructions support required. */
> CpuAVX512_VP2INTERSECT,
> + /* AMD AVX-512 BMM Instructions support required. */
> + CpuAVX512_BMM,
> /* TDX Instructions support required. */
> CpuTDX,
> /* Intel AVX VNNI Instructions support required. */
> @@ -497,6 +499,7 @@ typedef union i386_cpu_flags
> unsigned int cpuavx512_bitalg:1;
> unsigned int cpuavx512_bf16:1;
> unsigned int cpuavx512_vp2intersect:1;
> + unsigned int cpuavx512_bmm:1;
> unsigned int cputdx:1;
> unsigned int cpuavx_vnni:1;
> unsigned int cpuavx512_fp16:1;
> diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
> index b696f3c6f73..bc69d52225d 100644
> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3145,6 +3145,14 @@ vcvtneps2bf16<Vxy>, 0xf372, AVX_NE_CONVERT, Modrm|<Vxy:vex>|Space0F38|VexW0|NoSu
>
> // AVX-NE-CONVERT instructions end.
>
> +// AVX512_BMM instructions.
> +
> +vbmacor16x16x16, 0x80, AVX512_BMM, Modrm|EVexDYN|VexW0|Src1VVVV|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
> +vbmacxor16x16x16, 0x80, AVX512_BMM, Modrm|EVexDYN|VexW1|Src1VVVV|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM }
> +vbitrev, 0x81, AVX512_BMM, Modrm|EVexDYN|VexW0|Masking|Map6|Disp8ShiftVL|CheckOperandSize|NoSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM }
> +
> +// AVX512_BMM instructions end.
> +
> // ENQCMD instructions.
>
> enqcmd, 0xf20f38f8, ENQCMD, Modrm|AddrPrefixOpReg|NoSuf, { Unspecified|BaseIndex, Reg16|Reg32|Reg64 }
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