[PATCH] RISC-V: add machine architecture support

[Jerry Zhang Jian]

- The RISC-V profile has defined the following
  - Sm1p11, Machine Architecture v1.11
  - Sm1p12, Machine Architecture v1.12
- The RISC-V ISA manual has defined the following
  - Sm1p13, Machine Architecture v1.13

Ref: https://github.com/riscv/riscv-profiles/blob/5879c13c924ec5636995c5883f40337e83f6049a/src/rvm23-profile.adoc#L263
Ref: https://github.com/riscv/riscv-isa-manual/blob/584390d9d872835b1bc45ab9ea946b56db3ad485/src/machine.adoc#L4

Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
---
 bfd/elfxx-riscv.c                    | 3 +++
 gas/testsuite/gas/riscv/march-help.l | 1 +
 2 files changed, 4 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 93644423a3d..3d3d677dd7f 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1474,6 +1474,9 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"shvsatpa",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"shvstvala",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"shvstvecd",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"sm",		ISA_SPEC_CLASS_DRAFT,		1, 11, 0 },
+  {"sm",		ISA_SPEC_CLASS_DRAFT,		1, 12, 0 },
+  {"sm",		ISA_SPEC_CLASS_DRAFT,		1, 13, 0 },
   {"smaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smcsrind",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smcntrpmf",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 87faa87ce45..e376b271a2d 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -115,6 +115,7 @@ All available -march extensions for RISC-V:
 	shvsatpa                                1.0
 	shvstvala                               1.0
 	shvstvecd                               1.0
+	sm                                      1.11, 1.12, 1.13
 	smaia                                   1.0
 	smcsrind                                1.0
 	smcntrpmf                               1.0
-- 
2.49.0