[PATCH] RISC-V: Add supervisor architecture support

[Jerry Zhang Jian]

- The RISC-V profile has defined the following
  - Ss1p11, Supervisor Architecture v1.11
  - Ss1p12, Supervisor Architecture v1.12
  - Ss1p13, Supervisor Architecture v1.13
- Ref: https://github.com/riscv/riscv-profiles/blob/5879c13c924ec5636995c5883f40337e83f6049a/src/rvm23-profile.adoc#L265

Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
---
 bfd/elfxx-riscv.c                    | 3 +++
 gas/testsuite/gas/riscv/march-help.l | 1 +
 2 files changed, 4 insertions(+)

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 93644423a3d..4ddad07244b 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1482,6 +1482,9 @@ static struct riscv_supported_ext riscv_supported_std_s_ext[] =
   {"smrnmi",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smstateen",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"smdbltrp",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
+  {"ss",		ISA_SPEC_CLASS_DRAFT,		1, 11, 0 },
+  {"ss",		ISA_SPEC_CLASS_DRAFT,		1, 12, 0 },
+  {"ss",		ISA_SPEC_CLASS_DRAFT,		1, 13, 0 },
   {"ssaia",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"ssccptr",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
   {"sscsrind",		ISA_SPEC_CLASS_DRAFT,		1, 0, 0 },
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 87faa87ce45..18797e26a5d 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -123,6 +123,7 @@ All available -march extensions for RISC-V:
 	smrnmi                                  1.0
 	smstateen                               1.0
 	smdbltrp                                1.0
+	ss                                      1.11, 1.12, 1.13
 	ssaia                                   1.0
 	ssccptr                                 1.0
 	sscsrind                                1.0
-- 
2.49.0