[PATCH] RISC-V: add Smrnmi 1.0 instruction support

[Nelson Chu]

Okay, I also added the missing support in riscv_multi_subset_supports_ext,
and mentioned the encoding from riscv-opcodes tool.  Committed.

Nelson

On Tue, Mar 25, 2025 at 12:33 AM Jerry Zhang Jian <
jerry.zhangjian@sifive.com> wrote:

> Add instruction `mnret' support
>
> Ref:
> https://github.com/riscv/riscv-isa-manual/blob/bb8b9127f81965eeff2d150c211d1c89376591c4/src/rnmi.adoc
>
> bfd/ChangeLog:
>     * elfxx-riscv.c: Add new Smrnmi instruction class handling
>
> gas/ChangeLog:
>     * testsuite/gas/riscv/smrnmi.s: New test for mnret
>     * testsuite/gas/riscv/rmrnmi.d: Likewise
>
> include/ChangeLog:
>     * opcode/ricsv-opc.h: Add MATCH_MNRET, MASK_MNRET
>     * opcode/riscv.h: Add new instruction class
>
> opcodes/ChangeLog:
>     * riscv-opc.c: Add `mnret' instruction
>
> Signed-off-by: Jerry Zhang Jian <jerry.zhangjian@sifive.com>
> ---
>  bfd/elfxx-riscv.c                |  2 ++
>  gas/testsuite/gas/riscv/smrnmi.d | 10 ++++++++++
>  gas/testsuite/gas/riscv/smrnmi.s |  1 +
>  include/opcode/riscv-opc.h       |  5 +++++
>  include/opcode/riscv.h           |  1 +
>  opcodes/riscv-opc.c              |  3 +++
>  6 files changed, 22 insertions(+)
>  create mode 100644 gas/testsuite/gas/riscv/smrnmi.d
>  create mode 100644 gas/testsuite/gas/riscv/smrnmi.s
>
> diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
> index 92e024bbe35..7dc80d12cbc 100644
> --- a/bfd/elfxx-riscv.c
> +++ b/bfd/elfxx-riscv.c
> @@ -2801,6 +2801,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t
> *rps,
>      case INSN_CLASS_SMCTR_OR_SSCTR:
>        return (riscv_subset_supports (rps, "smctr")
>               || riscv_subset_supports (rps, "ssctr"));
> +    case INSN_CLASS_SMRNMI:
> +      return riscv_subset_supports (rps, "smrnmi");
>      case INSN_CLASS_SVINVAL:
>        return riscv_subset_supports (rps, "svinval");
>      case INSN_CLASS_H:
> diff --git a/gas/testsuite/gas/riscv/smrnmi.d
> b/gas/testsuite/gas/riscv/smrnmi.d
> new file mode 100644
> index 00000000000..e0659be53c9
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/smrnmi.d
> @@ -0,0 +1,10 @@
> +#as: -march=rv32i_smrnmi
> +#source: smrnmi.s
> +#objdump: -d
> +
> +.*:[   ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <.text>:
> +[      ]+[0-9a-f]+:[   ]+70200073[     ]+mnret
> diff --git a/gas/testsuite/gas/riscv/smrnmi.s
> b/gas/testsuite/gas/riscv/smrnmi.s
> new file mode 100644
> index 00000000000..085c10deaf0
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/smrnmi.s
> @@ -0,0 +1 @@
> +    mnret
> diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
> index 1f56317e255..fea49481498 100644
> --- a/include/opcode/riscv-opc.h
> +++ b/include/opcode/riscv-opc.h
> @@ -2311,6 +2311,9 @@
>  /* Smctr/Ssctr instruction.  */
>  #define MATCH_SCTRCLR 0x10400073
>  #define MASK_SCTRCLR 0xffffffff
> +/* Smrnmi instruction.  */
> +#define MATCH_MNRET 0x70200073
> +#define MASK_MNRET 0xffffffff
>  /* Svinval instruction.  */
>  #define MATCH_SINVAL_VMA 0x16000073
>  #define MASK_SINVAL_VMA 0xfe007fff
> @@ -4808,6 +4811,8 @@ DECLARE_INSN(cm_jt, MATCH_CM_JT, MASK_CM_JT)
>  DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT)
>  /* Smctr/Ssctr instruction.  */
>  DECLARE_INSN(sctrclr, MATCH_SCTRCLR, MASK_SCTRCLR)
> +/* Smrnmi instruction */
> +DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)
>  /* Vendor-specific (T-Head) XTheadBa instructions.  */
>  DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)
>  /* Vendor-specific (T-Head) XTheadBb instructions.  */
> diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
> index 1f4bede428e..d76bcdb295c 100644
> --- a/include/opcode/riscv.h
> +++ b/include/opcode/riscv.h
> @@ -526,6 +526,7 @@ enum riscv_insn_class
>    INSN_CLASS_ZCMP,
>    INSN_CLASS_ZCMT,
>    INSN_CLASS_SMCTR_OR_SSCTR,
> +  INSN_CLASS_SMRNMI,
>    INSN_CLASS_SVINVAL,
>    INSN_CLASS_ZICBOM,
>    INSN_CLASS_ZICBOP,
> diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
> index b83dcabf7fc..e07f72b89f2 100644
> --- a/opcodes/riscv-opc.c
> +++ b/opcodes/riscv-opc.c
> @@ -2305,6 +2305,9 @@ const struct riscv_opcode riscv_opcodes[] =
>  {"hinval.vvma",     0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_VVMA,
> MASK_HINVAL_VVMA, match_opcode, 0 },
>  {"hinval.gvma",     0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_GVMA,
> MASK_HINVAL_GVMA, match_opcode, 0 },
>
> +/* Smrnmi instruction */
> +{"mnret", 0, INSN_CLASS_SMRNMI, "", MATCH_MNRET, MASK_MNRET,
> match_opcode, 0 },
> +
>  /* Hypervisor instructions.  */
>  {"hfence.vvma", 0, INSN_CLASS_H, "",       MATCH_HFENCE_VVMA,
> MASK_HFENCE_VVMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS },
>  {"hfence.vvma", 0, INSN_CLASS_H, "s",      MATCH_HFENCE_VVMA,
> MASK_HFENCE_VVMA|MASK_RS2, match_opcode, INSN_ALIAS },
> --
> 2.46.0
>
>
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <https://sourceware.org/pipermail/binutils/attachments/20250326/9fe47fbe/attachment.htm>