<div dir="ltr">Okay, I also added the missing support in riscv_multi_subset_supports_ext, and mentioned the encoding from riscv-opcodes tool. Committed.<div><br></div><div>Nelson</div></div><br><div class="gmail_quote gmail_quote_container"><div dir="ltr" class="gmail_attr">On Tue, Mar 25, 2025 at 12:33 AM Jerry Zhang Jian <<a href="mailto:jerry.zhangjian@sifive.com">jerry.zhangjian@sifive.com</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex">Add instruction `mnret' support<br>
<br>
Ref: <a href="https://github.com/riscv/riscv-isa-manual/blob/bb8b9127f81965eeff2d150c211d1c89376591c4/src/rnmi.adoc" rel="noreferrer" target="_blank">https://github.com/riscv/riscv-isa-manual/blob/bb8b9127f81965eeff2d150c211d1c89376591c4/src/rnmi.adoc</a><br>
<br>
bfd/ChangeLog:<br>
* elfxx-riscv.c: Add new Smrnmi instruction class handling<br>
<br>
gas/ChangeLog:<br>
* testsuite/gas/riscv/smrnmi.s: New test for mnret<br>
* testsuite/gas/riscv/rmrnmi.d: Likewise<br>
<br>
include/ChangeLog:<br>
* opcode/ricsv-opc.h: Add MATCH_MNRET, MASK_MNRET<br>
* opcode/riscv.h: Add new instruction class<br>
<br>
opcodes/ChangeLog:<br>
* riscv-opc.c: Add `mnret' instruction<br>
<br>
Signed-off-by: Jerry Zhang Jian <<a href="mailto:jerry.zhangjian@sifive.com" target="_blank">jerry.zhangjian@sifive.com</a>><br>
---<br>
bfd/elfxx-riscv.c | 2 ++<br>
gas/testsuite/gas/riscv/smrnmi.d | 10 ++++++++++<br>
gas/testsuite/gas/riscv/smrnmi.s | 1 +<br>
include/opcode/riscv-opc.h | 5 +++++<br>
include/opcode/riscv.h | 1 +<br>
opcodes/riscv-opc.c | 3 +++<br>
6 files changed, 22 insertions(+)<br>
create mode 100644 gas/testsuite/gas/riscv/smrnmi.d<br>
create mode 100644 gas/testsuite/gas/riscv/smrnmi.s<br>
<br>
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c<br>
index 92e024bbe35..7dc80d12cbc 100644<br>
--- a/bfd/elfxx-riscv.c<br>
+++ b/bfd/elfxx-riscv.c<br>
@@ -2801,6 +2801,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,<br>
case INSN_CLASS_SMCTR_OR_SSCTR:<br>
return (riscv_subset_supports (rps, "smctr")<br>
|| riscv_subset_supports (rps, "ssctr"));<br>
+ case INSN_CLASS_SMRNMI:<br>
+ return riscv_subset_supports (rps, "smrnmi");<br>
case INSN_CLASS_SVINVAL:<br>
return riscv_subset_supports (rps, "svinval");<br>
case INSN_CLASS_H:<br>
diff --git a/gas/testsuite/gas/riscv/smrnmi.d b/gas/testsuite/gas/riscv/smrnmi.d<br>
new file mode 100644<br>
index 00000000000..e0659be53c9<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/smrnmi.d<br>
@@ -0,0 +1,10 @@<br>
+#as: -march=rv32i_smrnmi<br>
+#source: smrnmi.s<br>
+#objdump: -d<br>
+<br>
+.*:[ ]+file format .*<br>
+<br>
+Disassembly of section .text:<br>
+<br>
+0+000 <.text>:<br>
+[ ]+[0-9a-f]+:[ ]+70200073[ ]+mnret<br>
diff --git a/gas/testsuite/gas/riscv/smrnmi.s b/gas/testsuite/gas/riscv/smrnmi.s<br>
new file mode 100644<br>
index 00000000000..085c10deaf0<br>
--- /dev/null<br>
+++ b/gas/testsuite/gas/riscv/smrnmi.s<br>
@@ -0,0 +1 @@<br>
+ mnret<br>
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h<br>
index 1f56317e255..fea49481498 100644<br>
--- a/include/opcode/riscv-opc.h<br>
+++ b/include/opcode/riscv-opc.h<br>
@@ -2311,6 +2311,9 @@<br>
/* Smctr/Ssctr instruction. */<br>
#define MATCH_SCTRCLR 0x10400073<br>
#define MASK_SCTRCLR 0xffffffff<br>
+/* Smrnmi instruction. */<br>
+#define MATCH_MNRET 0x70200073<br>
+#define MASK_MNRET 0xffffffff<br>
/* Svinval instruction. */<br>
#define MATCH_SINVAL_VMA 0x16000073<br>
#define MASK_SINVAL_VMA 0xfe007fff<br>
@@ -4808,6 +4811,8 @@ DECLARE_INSN(cm_jt, MATCH_CM_JT, MASK_CM_JT)<br>
DECLARE_INSN(cm_jalt, MATCH_CM_JALT, MASK_CM_JALT)<br>
/* Smctr/Ssctr instruction. */<br>
DECLARE_INSN(sctrclr, MATCH_SCTRCLR, MASK_SCTRCLR)<br>
+/* Smrnmi instruction */<br>
+DECLARE_INSN(mnret, MATCH_MNRET, MASK_MNRET)<br>
/* Vendor-specific (T-Head) XTheadBa instructions. */<br>
DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL)<br>
/* Vendor-specific (T-Head) XTheadBb instructions. */<br>
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h<br>
index 1f4bede428e..d76bcdb295c 100644<br>
--- a/include/opcode/riscv.h<br>
+++ b/include/opcode/riscv.h<br>
@@ -526,6 +526,7 @@ enum riscv_insn_class<br>
INSN_CLASS_ZCMP,<br>
INSN_CLASS_ZCMT,<br>
INSN_CLASS_SMCTR_OR_SSCTR,<br>
+ INSN_CLASS_SMRNMI,<br>
INSN_CLASS_SVINVAL,<br>
INSN_CLASS_ZICBOM,<br>
INSN_CLASS_ZICBOP,<br>
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c<br>
index b83dcabf7fc..e07f72b89f2 100644<br>
--- a/opcodes/riscv-opc.c<br>
+++ b/opcodes/riscv-opc.c<br>
@@ -2305,6 +2305,9 @@ const struct riscv_opcode riscv_opcodes[] =<br>
{"hinval.vvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_VVMA, MASK_HINVAL_VVMA, match_opcode, 0 },<br>
{"hinval.gvma", 0, INSN_CLASS_SVINVAL, "s,t", MATCH_HINVAL_GVMA, MASK_HINVAL_GVMA, match_opcode, 0 },<br>
<br>
+/* Smrnmi instruction */<br>
+{"mnret", 0, INSN_CLASS_SMRNMI, "", MATCH_MNRET, MASK_MNRET, match_opcode, 0 },<br>
+<br>
/* Hypervisor instructions. */<br>
{"hfence.vvma", 0, INSN_CLASS_H, "", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA|MASK_RS1|MASK_RS2, match_opcode, INSN_ALIAS },<br>
{"hfence.vvma", 0, INSN_CLASS_H, "s", MATCH_HFENCE_VVMA, MASK_HFENCE_VVMA|MASK_RS2, match_opcode, INSN_ALIAS },<br>
-- <br>
2.46.0<br>
<br>
</blockquote></div>