[PATCH v1] aarch64: add missing virtual GICv3 CPU interface System registers

[Alice Carlotti]

On Mon, Jul 21, 2025 at 05:25:49PM +0100, Matthieu Longo wrote:
> Aliases to GIC CPU interface system registers were missed. Those registers
> are a part of Armv8-a, except for one that was introduced from Armv8.8-a.
> 
> From Armv8-a:
> - icv_ap0r[0-3]_el1
> - icv_ap1r[0-3]_el1
> - icv_bpr0_el1
> - icv_bpr1_el1
> - icv_ctlr_el1
> - icv_dir_el1 (WO)
> - icv_eoir0_el1 (WO)
> - icv_eoir1_el1 (WO)
> - icv_hppir0_el1 (RO)
> - icv_hppir1_el1 (RO)
> - icv_iar0_el1 (RO)
> - icv_iar1_el1 (RO)
> - icv_igrpen0_el1
> - icv_igrpen1_el1
> - icv_pmr_el1
> - icv_rpr_el1 (RO)
> 
> From Armv8.8-a:
> - icv_nmiar1_el1 (RO)

There's a difference between system registers and system register accessors.
Architecturally we have pairs of system registers icc_* and icv_*, but they are
both accessed using the icc_* accessors (with the values of PSTATE.EL and
HCR_EL2 helping to decide which system register is written or read by an
access).  So this patch is incorrect.

Incidentally, I'm currently in the middle of auditing our entire list of system
registers, and yesterday I was briefly confused by these system registers as
well.

Alice