[PATCH v1] aarch64: add missing virtual GICv3 CPU interface System registers
Matthieu Longo
matthieu.longo@arm.com
Mon Jul 21 16:25:49 GMT 2025
Aliases to GIC CPU interface system registers were missed. Those registers
are a part of Armv8-a, except for one that was introduced from Armv8.8-a.
>From Armv8-a:
- icv_ap0r[0-3]_el1
- icv_ap1r[0-3]_el1
- icv_bpr0_el1
- icv_bpr1_el1
- icv_ctlr_el1
- icv_dir_el1 (WO)
- icv_eoir0_el1 (WO)
- icv_eoir1_el1 (WO)
- icv_hppir0_el1 (RO)
- icv_hppir1_el1 (RO)
- icv_iar0_el1 (RO)
- icv_iar1_el1 (RO)
- icv_igrpen0_el1
- icv_igrpen1_el1
- icv_pmr_el1
- icv_rpr_el1 (RO)
>From Armv8.8-a:
- icv_nmiar1_el1 (RO)
---
gas/testsuite/gas/aarch64/sysreg/sysreg-8.d | 38 +++++++++++++++++++++
gas/testsuite/gas/aarch64/sysreg/sysreg-8.s | 31 +++++++++++++++++
opcodes/aarch64-sys-regs.def | 23 +++++++++++++
3 files changed, 92 insertions(+)
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d
index 8a1b07fdbfb..a3cbcf276ac 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.d
@@ -50,6 +50,42 @@ Disassembly of section \.text:
[^:]*: d538ccc0 mrs x0, icc_igrpen0_el1
[^:]*: d518cce0 msr icc_igrpen1_el1, x0
[^:]*: d538cce0 mrs x0, icc_igrpen1_el1
+[^:]*: d518c880 msr icc_ap0r0_el1, x0
+[^:]*: d538c880 mrs x0, icc_ap0r0_el1
+[^:]*: d518c8a0 msr icc_ap0r1_el1, x0
+[^:]*: d538c8a0 mrs x0, icc_ap0r1_el1
+[^:]*: d518c8c0 msr icc_ap0r2_el1, x0
+[^:]*: d538c8c0 mrs x0, icc_ap0r2_el1
+[^:]*: d518c8e0 msr icc_ap0r3_el1, x0
+[^:]*: d538c8e0 mrs x0, icc_ap0r3_el1
+[^:]*: d518c900 msr icc_ap1r0_el1, x0
+[^:]*: d538c900 mrs x0, icc_ap1r0_el1
+[^:]*: d518c920 msr icc_ap1r1_el1, x0
+[^:]*: d538c920 mrs x0, icc_ap1r1_el1
+[^:]*: d518c940 msr icc_ap1r2_el1, x0
+[^:]*: d538c940 mrs x0, icc_ap1r2_el1
+[^:]*: d518c960 msr icc_ap1r3_el1, x0
+[^:]*: d538c960 mrs x0, icc_ap1r3_el1
+[^:]*: d518c860 msr icc_bpr0_el1, x0
+[^:]*: d538c860 mrs x0, icc_bpr0_el1
+[^:]*: d518cc60 msr icc_bpr1_el1, x0
+[^:]*: d538cc60 mrs x0, icc_bpr1_el1
+[^:]*: d518cc80 msr icc_ctlr_el1, x0
+[^:]*: d538cc80 mrs x0, icc_ctlr_el1
+[^:]*: d518cb20 msr icc_dir_el1, x0
+[^:]*: d518c820 msr icc_eoir0_el1, x0
+[^:]*: d518cc20 msr icc_eoir1_el1, x0
+[^:]*: d538c840 mrs x0, icc_hppir0_el1
+[^:]*: d538cc40 mrs x0, icc_hppir1_el1
+[^:]*: d538c800 mrs x0, icc_iar0_el1
+[^:]*: d538cc00 mrs x0, icc_iar1_el1
+[^:]*: d518ccc0 msr icc_igrpen0_el1, x0
+[^:]*: d538ccc0 mrs x0, icc_igrpen0_el1
+[^:]*: d518cce0 msr icc_igrpen1_el1, x0
+[^:]*: d538cce0 mrs x0, icc_igrpen1_el1
+[^:]*: d5184600 msr icc_pmr_el1, x0
+[^:]*: d5384600 mrs x0, icc_pmr_el1
+[^:]*: d538cb60 mrs x0, icc_rpr_el1
[^:]*: d51cc800 msr ich_ap0r0_el2, x0
[^:]*: d53cc800 mrs x0, ich_ap0r0_el2
[^:]*: d51cc820 msr ich_ap0r1_el2, x0
@@ -291,6 +327,8 @@ Disassembly of section \.text:
[^:]*: d5389920 mrs x0, pmsnevfr_el1
[^:]*: d51c1240 msr hcrx_el2, x0
[^:]*: d53c1240 mrs x0, hcrx_el2
+[^:]*: d538c9a0 mrs x0, icc_nmiar1_el1
+[^:]*: d538c9a0 mrs x0, icc_nmiar1_el1
[^:]*: d518d0c0 msr rcwmask_el1, x0
[^:]*: d538d0c0 mrs x0, rcwmask_el1
[^:]*: d518d060 msr rcwsmask_el1, x0
diff --git a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s
index 0cf1178542a..ecd3362f269 100644
--- a/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s
+++ b/gas/testsuite/gas/aarch64/sysreg/sysreg-8.s
@@ -6,6 +6,7 @@
rw_sys_reg id_mmfr5_el1 w=0
rw_sys_reg id_isar6_el1 w=0
+ /* GIC CPU interface System register. */
rw_sys_reg icc_pmr_el1
rw_sys_reg icc_iar0_el1 w=0
rw_sys_reg icc_eoir0_el1 r=0
@@ -31,6 +32,32 @@
rw_sys_reg icc_ctlr_el1
rw_sys_reg icc_igrpen0_el1
rw_sys_reg icc_igrpen1_el1
+
+ /* Virtual GIC CPU interface System register. */
+ rw_sys_reg icv_ap0r0_el1
+ rw_sys_reg icv_ap0r1_el1
+ rw_sys_reg icv_ap0r2_el1
+ rw_sys_reg icv_ap0r3_el1
+ rw_sys_reg icv_ap1r0_el1
+ rw_sys_reg icv_ap1r1_el1
+ rw_sys_reg icv_ap1r2_el1
+ rw_sys_reg icv_ap1r3_el1
+ rw_sys_reg icv_bpr0_el1
+ rw_sys_reg icv_bpr1_el1
+ rw_sys_reg icv_ctlr_el1
+ rw_sys_reg icv_dir_el1 r=0
+ rw_sys_reg icv_eoir0_el1 r=0
+ rw_sys_reg icv_eoir1_el1 r=0
+ rw_sys_reg icv_hppir0_el1 w=0
+ rw_sys_reg icv_hppir1_el1 w=0
+ rw_sys_reg icv_iar0_el1 w=0
+ rw_sys_reg icv_iar1_el1 w=0
+ rw_sys_reg icv_igrpen0_el1
+ rw_sys_reg icv_igrpen1_el1
+ rw_sys_reg icv_pmr_el1
+ rw_sys_reg icv_rpr_el1 w=0
+
+ /* Hypervisor control registers. */
rw_sys_reg ich_ap0r0_el2
rw_sys_reg ich_ap0r1_el2
rw_sys_reg ich_ap0r2_el2
@@ -177,6 +204,10 @@
rw_sys_reg pmsnevfr_el1
rw_sys_reg hcrx_el2
+ .arch armv8.8-a
+ rw_sys_reg icc_nmiar1_el1 w=0
+ rw_sys_reg icv_nmiar1_el1 w=0
+
.arch armv8-a+the
rw_sys_reg rcwmask_el1
diff --git a/opcodes/aarch64-sys-regs.def b/opcodes/aarch64-sys-regs.def
index 5cb2342ba9b..dd4e7ed3e0b 100644
--- a/opcodes/aarch64-sys-regs.def
+++ b/opcodes/aarch64-sys-regs.def
@@ -517,6 +517,29 @@
SYSREG ("ich_misr_el2", CPENC (3,4,12,11,2), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("ich_vmcr_el2", CPENC (3,4,12,11,7), 0, AARCH64_NO_FEATURES)
SYSREG ("ich_vtr_el2", CPENC (3,4,12,11,1), F_REG_READ, AARCH64_NO_FEATURES)
+ SYSREG ("icv_ap0r0_el1", CPENC (3,0,12,8,4), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_ap0r1_el1", CPENC (3,0,12,8,5), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_ap0r2_el1", CPENC (3,0,12,8,6), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_ap0r3_el1", CPENC (3,0,12,8,7), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_ap1r0_el1", CPENC (3,0,12,9,0), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_ap1r1_el1", CPENC (3,0,12,9,1), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_ap1r2_el1", CPENC (3,0,12,9,2), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_ap1r3_el1", CPENC (3,0,12,9,3), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_bpr0_el1", CPENC (3,0,12,8,3), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_bpr1_el1", CPENC (3,0,12,12,3), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_ctlr_el1", CPENC (3,0,12,12,4), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_dir_el1", CPENC (3,0,12,11,1), F_REG_WRITE|F_REG_ALIAS,AARCH64_NO_FEATURES)
+ SYSREG ("icv_eoir0_el1", CPENC (3,0,12,8,1), F_REG_WRITE|F_REG_ALIAS,AARCH64_NO_FEATURES)
+ SYSREG ("icv_eoir1_el1", CPENC (3,0,12,12,1), F_REG_WRITE|F_REG_ALIAS,AARCH64_NO_FEATURES)
+ SYSREG ("icv_hppir0_el1", CPENC (3,0,12,8,2), F_REG_READ|F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_hppir1_el1", CPENC (3,0,12,12,2), F_REG_READ|F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_iar0_el1", CPENC (3,0,12,8,0), F_REG_READ|F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_iar1_el1", CPENC (3,0,12,12,0), F_REG_READ|F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_igrpen0_el1", CPENC (3,0,12,12,6), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_igrpen1_el1", CPENC (3,0,12,12,7), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_nmiar1_el1", CPENC (3,0,12,9,5), F_REG_READ|F_ARCHEXT|F_REG_ALIAS, AARCH64_FEATURE (V8_8A))
+ SYSREG ("icv_pmr_el1", CPENC (3,0,4,6,0), F_REG_ALIAS, AARCH64_NO_FEATURES)
+ SYSREG ("icv_rpr_el1", CPENC (3,0,12,11,3), F_REG_READ|F_REG_ALIAS, AARCH64_NO_FEATURES)
SYSREG ("id_aa64afr0_el1", CPENC (3,0,0,5,4), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64afr1_el1", CPENC (3,0,0,5,5), F_REG_READ, AARCH64_NO_FEATURES)
SYSREG ("id_aa64dfr0_el1", CPENC (3,0,0,5,0), F_REG_READ, AARCH64_NO_FEATURES)
--
2.50.1
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