[PATCH 1/4] RISC-V: Added testcase to show the current rvc and xlen problems

[Nelson Chu]

Okay, thanks for the suggestion.

Nelson

On Fri, Jul 4, 2025 at 2:37 PM Kito Cheng <kito.cheng@gmail.com> wrote:

> Could you add some testcase with zcb? that might be an interesting
> case since zcb isn't really included in C-ext,
> but we may want to turn off when norvc.
>
> On Fri, Jul 4, 2025 at 1:43 PM Nelson Chu <nelson@rivosinc.com> wrote:
> >
> > ---
> >  gas/testsuite/gas/riscv/option-arch-rvc.d | 38 +++++++++++++++++++++++
> >  gas/testsuite/gas/riscv/option-arch-rvc.s | 35 +++++++++++++++++++++
> >  2 files changed, 73 insertions(+)
> >  create mode 100644 gas/testsuite/gas/riscv/option-arch-rvc.d
> >  create mode 100644 gas/testsuite/gas/riscv/option-arch-rvc.s
> >
> > diff --git a/gas/testsuite/gas/riscv/option-arch-rvc.d
> b/gas/testsuite/gas/riscv/option-arch-rvc.d
> > new file mode 100644
> > index 00000000000..767854689cb
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/option-arch-rvc.d
> > @@ -0,0 +1,38 @@
> > +#as: -misa-spec=2.2 -march=rv64i
> > +#source: option-arch-rvc.s
> > +#objdump: -d --syms --special-syms -Mno-aliases
> > +
> > +.*:[   ]+file format .*
> > +
> > +SYMBOL TABLE:
> > +0+00 l    d  .text     0+00 .text
> > +0+00 l    d  .data     0+00 .data
> > +0+00 l    d  .bss      0+00 .bss
> > +0+00 l       .text     0+00 \$xrv64i2p0_c2p0
> > +0+02 l       .text     0+00 \$xrv64i2p0
> > +0+06 l       .text     0+00 \$xrv32i2p0_f2p0_c2p0
> > +0+08 l       .text     0+00 \$xrv32i2p0_f2p0
> > +0+0c l       .text     0+00 \$xrv32i2p0_f2p0_d2p0_c2p0
> > +0+0e l       .text     0+00 \$xrv32i2p0_f2p0_d2p0
> > +0+12 l       .text     0+00 \$xrv32i2p0_f2p0_d2p0_zca1p0
> > +0+16 l       .text     0+00 \$xrv32i2p0_f2p0_zca1p0_zcf1p0
> > +0+1a l       .text     0+00 \$xrv32i2p0_f2p0_d2p0_zca1p0_zcd1p0
> > +0+0 l    d  .riscv.attributes  0+00 .riscv.attributes
> > +
> > +
> > +Disassembly of section .text:
> > +
> > +0+000 <.text>:
> > +[      ]+[0-9a-f]+:[   ]+0001[         ]+c\.addi[      ]+zero,0
> > +[      ]+[0-9a-f]+:[   ]+00000013[     ]+addi[         ]+zero,zero,0
> > +[      ]+[0-9a-f]+:[   ]+6108[         ]+c\.ld[        ]+a0,0\(a0\)
> > +[      ]+[0-9a-f]+:[   ]+00052507[     ]+flw[  ]+fa0,0\(a0\)
> > +[      ]+[0-9a-f]+:[   ]+2108[         ]+c\.fld[       ]+fa0,0\(a0\)
> > +[      ]+[0-9a-f]+:[   ]+00053507[     ]+fld[  ]+fa0,0\(a0\)
> > +[      ]+[0-9a-f]+:[   ]+0001[         ]+c\.addi[      ]+zero,0
> > +[      ]+[0-9a-f]+:[   ]+0001[         ]+c\.addi[      ]+zero,0
> > +[      ]+[0-9a-f]+:[   ]+6108[         ]+c\.ld[        ]+a0,0\(a0\)
> > +[      ]+[0-9a-f]+:[   ]+6108[         ]+c\.ld[        ]+a0,0\(a0\)
> > +[      ]+[0-9a-f]+:[   ]+2108[         ]+c\.fld[       ]+fa0,0\(a0\)
> > +[      ]+[0-9a-f]+:[   ]+2108[         ]+c\.fld[       ]+fa0,0\(a0\)
> > +#...
> > diff --git a/gas/testsuite/gas/riscv/option-arch-rvc.s
> b/gas/testsuite/gas/riscv/option-arch-rvc.s
> > new file mode 100644
> > index 00000000000..3e48bc5ad60
> > --- /dev/null
> > +++ b/gas/testsuite/gas/riscv/option-arch-rvc.s
> > @@ -0,0 +1,35 @@
> > +.option rvc
> > +nop
> > +.option norvc
> > +nop
> > +
> > +.option push
> > +.option arch, rv32i
> > +.option arch, +c,+f
> > +flw fa0, 0(a0)
> > +.option arch, -c
> > +flw fa0, 0(a0)
> > +.option pop
> > +
> > +.option arch, +c,+d
> > +fld fa0, 0(a0)
> > +.option arch, -c
> > +fld fa0, 0(a0)
> > +
> > +.option arch, +zca
> > +nop
> > +.option arch, -c
> > +nop
> > +
> > +.option push
> > +.option arch, rv32i
> > +.option arch, +zcf
> > +flw fa0, 0(a0)
> > +.option arch, -c
> > +flw fa0, 0(a0)
> > +.option pop
> > +
> > +.option arch, +zcd
> > +fld fa0, 0(a0)
> > +.option arch, -c
> > +fld fa0, 0(a0)
> > --
> > 2.39.5 (Apple Git-154)
> >
>
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