[PATCH v2] RISC-V: Fixed the broken .option norvc and .option arch, -c

[Nelson Chu]

---
 bfd/elfxx-riscv.c                             | 10 +++++++++-
 .../gas/riscv/option-arch-rvc-fail.d          |  3 +++
 .../gas/riscv/option-arch-rvc-fail.l          |  4 ++++
 .../gas/riscv/option-arch-rvc-fail.s          |  5 +++++
 gas/testsuite/gas/riscv/option-arch-rvc.d     | 19 ++++++++++++++-----
 gas/testsuite/gas/riscv/option-arch-rvc.s     | 10 ++++++++++
 6 files changed, 45 insertions(+), 6 deletions(-)
 create mode 100644 gas/testsuite/gas/riscv/option-arch-rvc-fail.d
 create mode 100644 gas/testsuite/gas/riscv/option-arch-rvc-fail.l
 create mode 100644 gas/testsuite/gas/riscv/option-arch-rvc-fail.s

diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 43d3c0d0884..8b9d73fcede 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -2707,7 +2707,15 @@ riscv_update_subset1 (riscv_parse_subset_t *rps,
 	}
 
       if (removed)
-	riscv_remove_subset (rps->subset_list, subset);
+	{
+	  riscv_remove_subset (rps->subset_list, subset);
+
+	  /* FIXME: This is a workaround that only make the c removal works,
+	     but should find a way to correct others.  */
+	  if (strcmp (subset, "c") == 0)
+	    riscv_update_subset (rps, "-zca,-zcd,-zcf,-zcb,-zce,-zcmp,-zcmt,"
+				      "-zcmop,-zclsd");
+	}
       else
 	{
 	  riscv_subset_t *isubset = NULL;
diff --git a/gas/testsuite/gas/riscv/option-arch-rvc-fail.d b/gas/testsuite/gas/riscv/option-arch-rvc-fail.d
new file mode 100644
index 00000000000..341ee44e1d0
--- /dev/null
+++ b/gas/testsuite/gas/riscv/option-arch-rvc-fail.d
@@ -0,0 +1,3 @@
+#as: -misa-spec=2.2
+#source: option-arch-rvc-fail.s
+#error_output: option-arch-rvc-fail.l
diff --git a/gas/testsuite/gas/riscv/option-arch-rvc-fail.l b/gas/testsuite/gas/riscv/option-arch-rvc-fail.l
new file mode 100644
index 00000000000..4d147c589f2
--- /dev/null
+++ b/gas/testsuite/gas/riscv/option-arch-rvc-fail.l
@@ -0,0 +1,4 @@
+.*Assembler messages:
+.*Error: unrecognized opcode `cm.push {ra},-64', extension `zcmp' required
+.*Error: unrecognized opcode `cm.jt 0', extension `zcmt' required
+.*Error: unrecognized opcode `c.mop.1', extension `zcmop' required
diff --git a/gas/testsuite/gas/riscv/option-arch-rvc-fail.s b/gas/testsuite/gas/riscv/option-arch-rvc-fail.s
new file mode 100644
index 00000000000..e79c17ae023
--- /dev/null
+++ b/gas/testsuite/gas/riscv/option-arch-rvc-fail.s
@@ -0,0 +1,5 @@
+.option arch, +zcmp,+zcmt,+zcmop
+.option arch, -c
+cm.push {ra}, -64
+cm.jt 0
+c.mop.1
diff --git a/gas/testsuite/gas/riscv/option-arch-rvc.d b/gas/testsuite/gas/riscv/option-arch-rvc.d
index 8e2fb4721ff..1c9430bbcc7 100644
--- a/gas/testsuite/gas/riscv/option-arch-rvc.d
+++ b/gas/testsuite/gas/riscv/option-arch-rvc.d
@@ -15,8 +15,13 @@ SYMBOL TABLE:
 0+0c l       .text	0+00 \$xrv64i2p0_f2p0_d2p0_c2p0
 0+0e l       .text	0+00 \$xrv64i2p0_f2p0_d2p0
 0+12 l       .text	0+00 \$xrv64i2p0_f2p0_d2p0_zca1p0
-0+16 l       .text	0+00 \$xrv32i2p0_f2p0_zca1p0_zcf1p0
-0+1a l       .text	0+00 \$xrv64i2p0_f2p0_d2p0_zca1p0_zcd1p0
+0+14 l       .text	0+00 \$xrv64i2p0_f2p0_d2p0
+0+18 l       .text	0+00 \$xrv32i2p0_f2p0_zca1p0_zcf1p0
+0+1a l       .text	0+00 \$xrv32i2p0_f2p0
+0+1e l       .text	0+00 \$xrv64i2p0_f2p0_d2p0_zca1p0_zcd1p0
+0+20 l       .text	0+00 \$xrv64i2p0_f2p0_d2p0
+0+24 l       .text	0+00 \$xrv32i2p0_zilsd1p0_zca1p0_zcb1p0_zclsd1p0
+0+28 l       .text	0+00 \$xrv32i2p0_zilsd1p0
 0+0 l    d  .riscv.attributes	0+00 .riscv.attributes
 
 
@@ -30,9 +35,13 @@ Disassembly of section .text:
 [ 	]+[0-9a-f]+:[ 	]+2108[ 	]+c\.fld[ 	]+fa0,0\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+00053507[ 	]+fld[ 	]+fa0,0\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+0001[ 	]+c\.addi[ 	]+zero,0
-[ 	]+[0-9a-f]+:[ 	]+0001[ 	]+c\.addi[ 	]+zero,0
-[ 	]+[0-9a-f]+:[ 	]+6108[ 	]+c\.flw[ 	]+fa0,0\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+00000013[ 	]+addi[ 	]+zero,zero,0
 [ 	]+[0-9a-f]+:[ 	]+6108[ 	]+c\.flw[ 	]+fa0,0\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+00052507[ 	]+flw[ 	]+fa0,0\(a0\)
 [ 	]+[0-9a-f]+:[ 	]+2108[ 	]+c\.fld[ 	]+fa0,0\(a0\)
-[ 	]+[0-9a-f]+:[ 	]+2108[ 	]+c\.fld[ 	]+fa0,0\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+00053507[ 	]+fld[ 	]+fa0,0\(a0\)
+[ 	]+[0-9a-f]+:[ 	]+8020[ 	]+c\.lbu[ 	]+s0,2\(s0\)
+[ 	]+[0-9a-f]+:[ 	]+6080[ 	]+c\.ld[ 	]+s0,0\(s1\)
+[ 	]+[0-9a-f]+:[ 	]+00244403[ 	]+lbu[ 	]+s0,2\(s0\)
+[ 	]+[0-9a-f]+:[ 	]+0004b403[ 	]+ld[ 	]+s0,0\(s1\)
 #...
diff --git a/gas/testsuite/gas/riscv/option-arch-rvc.s b/gas/testsuite/gas/riscv/option-arch-rvc.s
index 3e48bc5ad60..520f34ba0b0 100644
--- a/gas/testsuite/gas/riscv/option-arch-rvc.s
+++ b/gas/testsuite/gas/riscv/option-arch-rvc.s
@@ -33,3 +33,13 @@ flw fa0, 0(a0)
 fld fa0, 0(a0)
 .option arch, -c
 fld fa0, 0(a0)
+
+.option push
+.option arch, rv32i
+.option arch, +zcb,+zclsd
+lbu x8,2(x8)
+ld x8, 0(x9)
+.option arch, -c
+lbu x8,2(x8)
+ld x8, 0(x9)
+.option pop
-- 
2.39.5 (Apple Git-154)