Add AMD znver5 RMPREAD instruction

[Kalvakuntla, Umesh]

> > There's no true ModR/M byte in this insn; the 0xfe part of the opcode
> > already fully specifies what takes the place of the ModR/M byte.
> >
> > rmpupdate, 0xf20f01fe, SNP&x64, AddrPrefixOpReg|NoSuf, {
> > RegC|Unspecified, Acc|Qword }
> >
> > may be getting closer to what you want (but obviously this is
> > untested). This will require adjustments to the AddrPrefixOpReg
> > handling then, or maybe we even need an entirely new insn attribute
> > here. I would offer to take a stab, yet then I'd first need to have a
> > complete list of insns with their intended new operand combinations.
> > Aiui the two
> >
> >         rmpread %rax, (%rcx)
> >         rmpupdate (%rcx), %rax
> >
> > that you had in your earlier mail isn't the complete set.

Sure, please let us know your findings/pointers, or, if you'd be implementing it. 


> Hmm, going through all of them, it looks like it's really just these two which need the
> new behavior.

Okay, we found the same. Only these two are requiring segment overrides in SNP.


Regards,
Umesh