[PATCH 3/6] Regenerate files
Andrew Carlotti
andrew.carlotti@arm.com
Tue Jan 7 13:38:20 GMT 2025
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index bf01dc6b4214f43f5e9a8c7161145771d1b491a5..799825c25cbfaa0a049c0c2ced8431c7d2f3dd01 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -679,22 +679,22 @@ aarch64_insert_operand (const aarch64_operand *self,
case 230:
case 241:
case 245:
- case 250:
+ case 249:
+ case 257:
case 258:
case 259:
- case 260:
+ case 266:
case 267:
case 268:
case 269:
- case 270:
- case 304:
- case 308:
+ case 303:
+ case 307:
return aarch64_ins_regno (self, info, code, inst, errors);
case 6:
case 119:
case 120:
- case 314:
- case 317:
+ case 313:
+ case 316:
return aarch64_ins_none (self, info, code, inst, errors);
case 17:
return aarch64_ins_reg_extended (self, info, code, inst, errors);
@@ -709,7 +709,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 37:
case 38:
case 39:
- case 319:
+ case 318:
return aarch64_ins_reglane (self, info, code, inst, errors);
case 40:
case 41:
@@ -717,8 +717,9 @@ aarch64_insert_operand (const aarch64_operand *self,
case 231:
case 232:
case 235:
+ case 270:
case 271:
- case 272:
+ case 286:
case 287:
case 288:
case 289:
@@ -735,13 +736,12 @@ aarch64_insert_operand (const aarch64_operand *self,
case 300:
case 301:
case 302:
- case 303:
+ case 304:
case 305:
case 306:
- case 307:
+ case 308:
case 309:
case 310:
- case 311:
return aarch64_ins_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ins_reglist (self, info, code, inst, errors);
@@ -791,14 +791,14 @@ aarch64_insert_operand (const aarch64_operand *self,
case 210:
case 211:
case 212:
- case 273:
+ case 272:
+ case 311:
case 312:
- case 313:
+ case 314:
case 315:
- case 316:
- case 318:
+ case 317:
+ case 322:
case 323:
- case 324:
return aarch64_ins_imm (self, info, code, inst, errors);
case 52:
case 53:
@@ -947,7 +947,7 @@ aarch64_insert_operand (const aarch64_operand *self,
case 201:
case 202:
case 203:
- case 286:
+ case 285:
return aarch64_ins_sve_shrimm (self, info, code, inst, errors);
case 217:
case 218:
@@ -974,54 +974,53 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sve_index (self, info, code, inst, errors);
case 244:
case 246:
- case 266:
+ case 265:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case 247:
case 248:
+ case 250:
case 251:
case 252:
case 253:
case 254:
- case 255:
- case 265:
+ case 264:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
- case 249:
+ case 255:
case 256:
- case 257:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
+ case 260:
+ case 262:
+ case 273:
+ return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
case 261:
case 263:
- case 274:
- return aarch64_ins_sme_za_hv_tiles (self, info, code, inst, errors);
- case 262:
- case 264:
return aarch64_ins_sme_za_hv_tiles_range (self, info, code, inst, errors);
+ case 274:
case 275:
case 276:
case 277:
case 278:
case 279:
case 280:
- case 281:
return aarch64_ins_sme_za_array (self, info, code, inst, errors);
- case 282:
+ case 281:
return aarch64_ins_sme_addr_ri_u4xvl (self, info, code, inst, errors);
- case 283:
+ case 282:
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
- case 284:
+ case 283:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
- case 285:
+ case 284:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
+ case 319:
case 320:
case 321:
- case 322:
return aarch64_ins_x0_to_x30 (self, info, code, inst, errors);
+ case 324:
case 325:
case 326:
case 327:
- case 328:
return aarch64_ins_rcpc3_addr_opt_offset (self, info, code, inst, errors);
- case 329:
+ case 328:
return aarch64_ins_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 95344740328b4757afacd90b24ad3640baa81148..44188ad6529c2c667f43a98406fb1d9693286e50 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -34842,22 +34842,22 @@ aarch64_extract_operand (const aarch64_operand *self,
case 230:
case 241:
case 245:
- case 250:
+ case 249:
+ case 257:
case 258:
case 259:
- case 260:
+ case 266:
case 267:
case 268:
case 269:
- case 270:
- case 304:
- case 308:
+ case 303:
+ case 307:
return aarch64_ext_regno (self, info, code, inst, errors);
case 6:
case 119:
case 120:
- case 314:
- case 317:
+ case 313:
+ case 316:
return aarch64_ext_none (self, info, code, inst, errors);
case 11:
return aarch64_ext_regrt_sysins (self, info, code, inst, errors);
@@ -34877,7 +34877,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 37:
case 38:
case 39:
- case 319:
+ case 318:
return aarch64_ext_reglane (self, info, code, inst, errors);
case 40:
case 41:
@@ -34885,8 +34885,9 @@ aarch64_extract_operand (const aarch64_operand *self,
case 231:
case 232:
case 235:
+ case 270:
case 271:
- case 272:
+ case 286:
case 287:
case 288:
case 289:
@@ -34903,13 +34904,12 @@ aarch64_extract_operand (const aarch64_operand *self,
case 300:
case 301:
case 302:
- case 303:
+ case 304:
case 305:
case 306:
- case 307:
+ case 308:
case 309:
case 310:
- case 311:
return aarch64_ext_simple_index (self, info, code, inst, errors);
case 43:
return aarch64_ext_reglist (self, info, code, inst, errors);
@@ -34960,14 +34960,14 @@ aarch64_extract_operand (const aarch64_operand *self,
case 210:
case 211:
case 212:
- case 273:
+ case 272:
+ case 311:
case 312:
- case 313:
+ case 314:
case 315:
- case 316:
- case 318:
+ case 317:
+ case 322:
case 323:
- case 324:
return aarch64_ext_imm (self, info, code, inst, errors);
case 52:
case 53:
@@ -35118,7 +35118,7 @@ aarch64_extract_operand (const aarch64_operand *self,
case 201:
case 202:
case 203:
- case 286:
+ case 285:
return aarch64_ext_sve_shrimm (self, info, code, inst, errors);
case 217:
case 218:
@@ -35145,54 +35145,53 @@ aarch64_extract_operand (const aarch64_operand *self,
return aarch64_ext_sve_index (self, info, code, inst, errors);
case 244:
case 246:
- case 266:
+ case 265:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
case 247:
case 248:
+ case 250:
case 251:
case 252:
case 253:
case 254:
- case 255:
- case 265:
+ case 264:
return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
- case 249:
+ case 255:
case 256:
- case 257:
return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
+ case 260:
+ case 262:
+ case 273:
+ return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
case 261:
case 263:
- case 274:
- return aarch64_ext_sme_za_hv_tiles (self, info, code, inst, errors);
- case 262:
- case 264:
return aarch64_ext_sme_za_hv_tiles_range (self, info, code, inst, errors);
+ case 274:
case 275:
case 276:
case 277:
case 278:
case 279:
case 280:
- case 281:
return aarch64_ext_sme_za_array (self, info, code, inst, errors);
- case 282:
+ case 281:
return aarch64_ext_sme_addr_ri_u4xvl (self, info, code, inst, errors);
- case 283:
+ case 282:
return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
- case 284:
+ case 283:
return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
- case 285:
+ case 284:
return aarch64_ext_plain_shrimm (self, info, code, inst, errors);
+ case 319:
case 320:
case 321:
- case 322:
return aarch64_ext_x0_to_x30 (self, info, code, inst, errors);
+ case 324:
case 325:
case 326:
case 327:
- case 328:
return aarch64_ext_rcpc3_addr_opt_offset (self, info, code, inst, errors);
- case 329:
+ case 328:
return aarch64_ext_rcpc3_addr_offset (self, info, code, inst, errors);
default: assert (0); abort ();
}
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index ba6514b164916773d26d75e670ee4e3f6e4df5b3..526d1e24da1782d13e6fa6557331141f0e8888e3 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -273,7 +273,6 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REGLIST, "SVE_ZtxN", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zt}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn2}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zdn4}, "a list of SVE vector registers"},
- {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zdnx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZdnT, FLD_SME_Zdn2_0}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4}, "a list of SVE vector registers"},
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