[PATCH 2/6] aarch64: Remove redundant sme-lutv2 qualifiers and operands
Andrew Carlotti
andrew.carlotti@arm.com
Tue Jan 7 13:38:00 GMT 2025
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 3046d3d8b5e216bf621a96d5f23fdb0cb1562a8d..92e584d17a0cf1f7fd8284e8e86a07ea5ecb9cd2 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -6974,7 +6974,6 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_ZtxN:
case AARCH64_OPND_SME_Zdnx2:
case AARCH64_OPND_SME_Zdnx4:
- case AARCH64_OPND_SME_Zdnx4_STRIDED:
case AARCH64_OPND_SME_Zmx2:
case AARCH64_OPND_SME_Zmx4:
case AARCH64_OPND_SME_Znx2:
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index b02d4f89fb40401c7b148f72597b0b993d129139..61a5f36d87f2a7724add7b90448eae1f491e67d3 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -813,7 +813,6 @@ enum aarch64_opnd
AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
AARCH64_OPND_SME_Zdnx2, /* SVE vector register list from [4:1]*2. */
AARCH64_OPND_SME_Zdnx4, /* SVE vector register list from [4:2]*4. */
- AARCH64_OPND_SME_Zdnx4_STRIDED, /* SVE vector register list from [4:2]*4. */
AARCH64_OPND_SME_Zm, /* SVE vector register list in 4-bit Zm. */
AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */
AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index b644329ab734ed94f30d0343df3bf6dca33065f8..9ab9bdf512369d10737eb8b9b7a56a70922827f2 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -63,9 +63,7 @@ enum aarch64_field_kind
FLD_SME_ZAda_1b,
FLD_SME_ZAda_2b,
FLD_SME_ZAda_3b,
- FLD_SME_ZdnT,
FLD_SME_Zdn2,
- FLD_SME_Zdn2_0,
FLD_SME_Zdn4,
FLD_SME_Zm,
FLD_SME_Zm2,
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index fb609426140f657b98ba26b64399ff8ac2d5cbae..1ddd9ba02b2d9dd010959ff705d1aa1dd44a81b6 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -259,9 +259,7 @@ const aarch64_field fields[] =
{ 0, 1 }, /* SME_ZAda_1b: tile ZA0-ZA1. */
{ 0, 2 }, /* SME_ZAda_2b: tile ZA0-ZA3. */
{ 0, 3 }, /* SME_ZAda_3b: tile ZA0-ZA7. */
- { 4, 1 }, /* SME_ZdnT: upper bit of Zt, bit [4]. */
{ 1, 4 }, /* SME_Zdn2: Z0-Z31, multiple of 2, bits [4:1]. */
- { 0, 2 }, /* SME_Zdn2_0: lower 2 bits of Zt, bits [1:0]. */
{ 2, 3 }, /* SME_Zdn4: Z0-Z31, multiple of 4, bits [4:2]. */
{ 16, 4 }, /* SME_Zm: Z0-Z15, bits [19:16]. */
{ 17, 4 }, /* SME_Zm2: Z0-Z31, multiple of 2, bits [20:17]. */
@@ -2004,7 +2002,6 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
}
break;
- case AARCH64_OPND_SME_Zdnx4_STRIDED:
case AARCH64_OPND_SME_Ztx2_STRIDED:
case AARCH64_OPND_SME_Ztx4_STRIDED:
/* 2-register lists have a stride of 8 and 4-register lists
@@ -4342,7 +4339,6 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SVE_ZtxN:
case AARCH64_OPND_SME_Zdnx2:
case AARCH64_OPND_SME_Zdnx4:
- case AARCH64_OPND_SME_Zdnx4_STRIDED:
case AARCH64_OPND_SME_Zmx2:
case AARCH64_OPND_SME_Zmx4:
case AARCH64_OPND_SME_Znx2:
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 455d193ac6930a25cc35b3434e3e6ec4ca825ce8..15b1593b9ffe4dd620c4558f8d0126792b79314a 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1826,13 +1826,6 @@
{ \
QLF2(S_S,NIL), \
}
-/* e.g. movt ZT0{[<offs>, MUL VL]}, <Zt> */
-/* The second operand doesn't have a qualifier and
- is checked separetely during encoding. */
-#define OP_SVE_SU_Q \
-{ \
- QLF2(S_Q,NIL), \
-}
#define OP_SVE_SUS \
{ \
QLF3(S_S,NIL,S_S), \
@@ -2081,13 +2074,6 @@
QLF3(S_S,NIL,W), \
QLF3(S_D,NIL,X), \
}
-/* e.g. luti4 { <Zd1>.B-<Zd4>.B }, ZT0, { <Zn1>-<Zn2> } */
-/* The second and third operands don't have qualifiers and
- are checked separetely during encoding. */
-#define OP_SVE_VUU_B \
-{ \
- QLF3(S_B,NIL,NIL), \
-}
#define OP_SVE_VUU_BH \
{ \
QLF3(S_B,NIL,NIL), \
@@ -6812,8 +6798,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
LUT_SVE2_INSN ("luti4", 0x4520bc00, 0xff20fc00, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm2_22_INDEX), OP_SVE_HHU, F_OD(1), 0),
/* SME2 lutv2. */
- LUTv2_SME2_INSN ("luti4", 0xc08b0000, 0xffffcc23, sme_size_12_b, OP3 (SME_Zdnx4, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_VUU_B, F_STRICT | 0),
- LUTv2_SME2p1_INSN ("luti4", 0xc09b0000, 0xffffcc2c, sme_size_12_b, OP3 (SME_Zdnx4_STRIDED, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_VUU_B, F_STRICT | 0),
+ LUTv2_SME2_INSN ("luti4", 0xc08b0000, 0xffffcc23, sme_size_12_b, OP3 (SME_Zdnx4, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_BUU, F_STRICT | 0),
+ LUTv2_SME2p1_INSN ("luti4", 0xc09b0000, 0xffffcc2c, sme_size_12_b, OP3 (SME_Ztx4_STRIDED, SME_ZT0, SME_Znx2_BIT_INDEX), OP_SVE_BUU, F_STRICT | 0),
LUTv2_SME2_INSN ("movt", 0xc04f03e0, 0xffffcfe0, sme_misc, OP2 (SME_ZT0_INDEX2_12, SVE_Zt), {}, 0),
/* SME FP16 ZA-targeting addition instructions. */
SME_F16F16_F8F16_INSNC("fadd", 0xc1a41c00, 0xffff9c38, sme_misc, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_HH, F_OD (2), 0),
@@ -7426,9 +7412,6 @@ const struct aarch64_opcode aarch64_opcode_table[] =
F(FLD_SME_Zdn2), "a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zdnx4", 4 << OPD_F_OD_LSB, \
F(FLD_SME_Zdn4), "a list of SVE vector registers") \
- Y(SVE_REGLIST, sve_strided_reglist, "SME_Zdnx4_STRIDED", \
- 4 << OPD_F_OD_LSB, F(FLD_SME_ZdnT, FLD_SME_Zdn2_0), \
- "a list of SVE vector registers") \
Y(SVE_REG, regno, "SME_Zm", 0, F(FLD_SME_Zm), \
"an SVE vector register") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \
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