[PATCH v6] AArch64: Add FEAT_SVE2p3 and FEAT_SME2p3 instructions.
Alice Carlotti
alice.carlotti@arm.com
Sat Dec 27 14:10:59 GMT 2025
On Wed, Dec 17, 2025 at 12:31:04PM +0000, Sivan Shani wrote:
> This patch includes:
>
> - Flags for the FEAT_SVE2p3 and FEAT_SME2p3 features.
> - Instructions:
> - ADDQP
> - ADDSUBP
> - FCVTZSN
> - FCVTZUN
> - LUTI6 16-bit
> - LUTI6 8-bit
> - SABAL
> - SCVTF
> - SCVTFLT
> - SDOT vectors
> - SDOT indexed
> - SQRSHRN
> - SQRSHRUN
> - SQSHRN
> - SQSHRUN
> - SUBP
> - UABAL
> - UCVTF
> - UCVTFLT
> - UDOT vectors
> - UDOT indexed
> - UQRSHRN
> - UQSHRN
> - LUTI6 vector
> - LUTI6 table, four registers
> - LUTI6 table, single, 8-bit
>
> In addition, new operands:
> - OPND_SME_Zmx2_INDEX_22: an operand represents a list of vector registers with an index.
> - OPND_SME_Zn7xN_UNTYPED: an operand represents an untyped list of vector registers.
> ---
> gas/config/tc-aarch64.c | 35 +-
> gas/doc/c-aarch64.texi | 4 +
> gas/testsuite/gas/aarch64/illegal-memtag.l | 2 +-
> gas/testsuite/gas/aarch64/sme2p3-bad.d | 4 +
> gas/testsuite/gas/aarch64/sme2p3-bad.l | 13 +
> gas/testsuite/gas/aarch64/sme2p3-bad.s | 12 +
> gas/testsuite/gas/aarch64/sme2p3.d | 33 ++
> gas/testsuite/gas/aarch64/sme2p3.s | 25 +
> gas/testsuite/gas/aarch64/sve-invalid.l | 8 +-
> .../gas/aarch64/sve2-sme2-6-invalid.l | 16 +-
> gas/testsuite/gas/aarch64/sve2p3.d | 246 ++++++++++
> gas/testsuite/gas/aarch64/sve2p3.s | 238 +++++++++
> include/opcode/aarch64.h | 9 +
> opcodes/aarch64-asm-2.c | 4 +
> opcodes/aarch64-asm.c | 15 +
> opcodes/aarch64-asm.h | 1 +
> opcodes/aarch64-dis-2.c | 454 ++++++++++++++----
> opcodes/aarch64-dis.c | 19 +
> opcodes/aarch64-dis.h | 1 +
> opcodes/aarch64-opc-2.c | 3 +
> opcodes/aarch64-opc.c | 22 +
> opcodes/aarch64-opc.h | 1 +
> opcodes/aarch64-tbl-2.h | 28 ++
> opcodes/aarch64-tbl.h | 68 +++
> 24 files changed, 1153 insertions(+), 108 deletions(-)
> create mode 100644 gas/testsuite/gas/aarch64/sme2p3-bad.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2p3-bad.l
> create mode 100644 gas/testsuite/gas/aarch64/sme2p3-bad.s
> create mode 100644 gas/testsuite/gas/aarch64/sme2p3.d
> create mode 100644 gas/testsuite/gas/aarch64/sme2p3.s
> create mode 100644 gas/testsuite/gas/aarch64/sve2p3.d
> create mode 100644 gas/testsuite/gas/aarch64/sve2p3.s
Thanks, just a few small nits remaining. I've fixed these and pushed the patch
for you (along with your other patches).
>
> diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
> index 0ca54c3bd40..7af3fbc9c2e 100644
> --- a/gas/config/tc-aarch64.c
> +++ b/gas/config/tc-aarch64.c
> @@ -1394,6 +1394,11 @@ reg_type_mask (aarch64_reg_type reg_type)
> If HAS_QUALIFIER is false, the registers in the list must not have
> qualifiers or the list is invalid.
>
> + If EXPECT_INDEX is true, the register list must have an index,
> + or the list is invalid.
> + If EXPECT_INDEX is false, the register list must not have an index,
> + or the list is invalid.
> +
This last bit isn't quite correct. After rebasing on top of my recent change
to the function comments, I've adjusted this hunk to say:
- If the register list contains typed SIMD registers without an element count
- (e.g. "v0.h"), then the register list must be indexed.
+ If EXPECT_INDEX is true, or the register list contains typed SIMD registers
+ without an element count (e.g. "v0.h"), then the register list must be
+ indexed.
> The list contains one to four registers.
> Each register can be one of:
> <Vt>.<T>[<index>]
> @@ -1406,7 +1411,7 @@ reg_type_mask (aarch64_reg_type reg_type)
> static int
> parse_vector_reg_list (char **ccp, aarch64_reg_type type,
> struct vector_type_el *vectype,
> - bool has_qualifier)
> + bool has_qualifier, bool expect_index)
> {
> char *str = *ccp;
> int nb_regs;
> @@ -1415,7 +1420,6 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
> int in_range;
> int ret_val;
> bool error = false;
> - bool expect_index = false;
> unsigned int ptr_flags = PTR_IN_REGLIST;
>
> if (*str != '{')
> @@ -7023,9 +7027,9 @@ parse_operands (char *str, const aarch64_opcode *opcode)
> break;
>
> case AARCH64_OPND_SME_Znx2_BIT_INDEX:
> - // A vector register list encoding a bit index.
> + case AARCH64_OPND_SME_Zn7xN_UNTYPED:
> reg_type = REG_TYPE_Z;
> - val = parse_vector_reg_list (&str, reg_type, &vectype, false);
> + val = parse_vector_reg_list (&str, reg_type, &vectype, false, false);
> if (val == PARSE_FAIL)
> goto failure;
>
> @@ -7037,6 +7041,20 @@ parse_operands (char *str, const aarch64_opcode *opcode)
>
> break;
>
> + case AARCH64_OPND_SME_Zmx2_INDEX_22:
> + reg_type = REG_TYPE_Z;
> + val = parse_vector_reg_list (&str, reg_type, &vectype, false, true);
> + if (val == PARSE_FAIL)
> + goto failure;
> + if (! reg_list_valid_p (val, &info->reglist, reg_type))
> + {
> + set_fatal_syntax_error (_("invalid register list"));
> + goto failure;
> + }
> + info->reglist.has_index = 1;
> + info->reglist.index = vectype.index;
> + break;
> +
> case AARCH64_OPND_SVE_ZnxN:
> case AARCH64_OPND_SVE_ZtxN:
> case AARCH64_OPND_SME_Zdnx2:
> @@ -7077,7 +7095,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
> }
> else
> {
> - val = parse_vector_reg_list (&str, reg_type, &vectype, true);
> + val = parse_vector_reg_list (&str, reg_type, &vectype, true, false);
> if (val == PARSE_FAIL)
> goto failure;
>
> @@ -7108,7 +7126,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
> if (!(vectype.defined & NTA_HASTYPE))
> {
> if (reg_type == REG_TYPE_Z || reg_type == REG_TYPE_P)
> - set_fatal_syntax_error (_("missing type suffix"));
> + set_fatal_syntax_error (_("missing type suffix"));
This indentation change (tab -> spaces) is inccorect.
> goto failure;
> }
> }
> @@ -7175,6 +7193,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
> case AARCH64_OPND_SVE_SHLIMM_PRED:
> case AARCH64_OPND_SVE_SHLIMM_UNPRED:
> case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
> + case AARCH64_OPND_SME_SHRIMM3:
> case AARCH64_OPND_SME_SHRIMM4:
> case AARCH64_OPND_SME_SHRIMM5:
> case AARCH64_OPND_SVE_SHRIMM_PRED:
> @@ -10905,6 +10924,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
> {"ssve-fexpa", AARCH64_FEATURE (SSVE_FEXPA), AARCH64_FEATURE (SME2)},
> {"sme-tmop", AARCH64_FEATURE (SME_TMOP), AARCH64_FEATURE (SME2)},
> {"sme-mop4", AARCH64_FEATURE (SME_MOP4), AARCH64_FEATURE (SME2)},
> + {"sve2p3", AARCH64_FEATURE (SVE2p3), AARCH64_FEATURE (SVE2p2)},
> + {"sme2p3", AARCH64_FEATURE (SME2p3), AARCH64_FEATURES (2, SME2p2, SME_LUTv2)},
> {NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
> };
>
> @@ -10938,6 +10959,8 @@ static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
> {AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SVE2p1_SME2p1)},
> {AARCH64_FEATURE (SVE2p2), AARCH64_FEATURE (SVE2p2_SME2p2)},
> {AARCH64_FEATURE (SME2p2), AARCH64_FEATURES (2, SVE_SME2p2, SVE2p2_SME2p2)},
> + {AARCH64_FEATURE (SVE2p3), AARCH64_FEATURE (SVE2p3_SME2p3)},
> + {AARCH64_FEATURE (SME2p3), AARCH64_FEATURE (SVE2p3_SME2p3)},
> };
>
> static aarch64_feature_set
> diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
> index 9683d411ce9..bf9abbc478f 100644
> --- a/gas/doc/c-aarch64.texi
> +++ b/gas/doc/c-aarch64.texi
> @@ -319,6 +319,8 @@ automatically cause those extensions to be disabled.
> @tab Enable SME2.1.
> @item @code{sme2p2} @tab @code{sme2p1}
> @tab Enable SME2.2.
> +@item @code{sme2p3} @tab @code{sme2p2}
> + @tab Enable SME2.3.
> @item @code{ssbs} @tab
> @tab Enable Speculative Store Bypassing Safe state read and write.
> @item @code{ssve-aes} @tab @code{sme2}, @code{sve-aes}
> @@ -361,6 +363,8 @@ automatically cause those extensions to be disabled.
> @tab Enable SVE2.1.
> @item @code{sve2p2} @tab @code{sve2p1}
> @tab Enable SVE2.2.
> +@item @code{sve2p3} @tab @code{sve2p2}
> + @tab Enable SVE2.3.
> @item @code{the} @tab
> @tab Enable the Translation Hardening Extension.
> @item @code{tme} @tab
> diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
> index 476c345d366..9e9d6bf0dae 100644
> --- a/gas/testsuite/gas/aarch64/illegal-memtag.l
> +++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
> @@ -26,7 +26,7 @@
> [^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `gmi x1,xzr,x3'
> [^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `addg xzr,x2,#0,#0'
> [^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subg x1,xzr,#0,#0'
> -[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `subp sp,x1,x2'
> +[^:]*:[0-9]+: Error: expected an integer register or SVE vector register at operand 1 -- `subp sp,x1,x2'
> [^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subp x1,xzr,x2'
> [^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 3 -- `subp x1,x2,xzr'
> [^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `subps sp,x1,x2'
> diff --git a/gas/testsuite/gas/aarch64/sme2p3-bad.d b/gas/testsuite/gas/aarch64/sme2p3-bad.d
> new file mode 100644
> index 00000000000..9494011cac5
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sme2p3-bad.d
> @@ -0,0 +1,4 @@
> +#name: Negative test for the SME_ZmxN_INDEX_22, SME_Zn7xN_UNTYPED, SME_SHRIMM3 opernads
> +#as: -march=armv8-a+sme2p3
> +#source: sme2p3-bad.s
> +#error_output: sme2p3-bad.l
> diff --git a/gas/testsuite/gas/aarch64/sme2p3-bad.l b/gas/testsuite/gas/aarch64/sme2p3-bad.l
> new file mode 100644
> index 00000000000..36115ed0b00
> --- /dev/null
> +++ b/gas/testsuite/gas/aarch64/sme2p3-bad.l
> @@ -0,0 +1,13 @@
> +.*: Assembler messages:
> +.*: Error: expected index at operand 3 -- `luti6 {z0.h-z3.h},{z0.h-z1.h},{z0-z1}'
> +.*: Error: too many registers in vector register list at operand 3 -- `luti6 {z0.h-z3.h},{z0.h-z1.h},{z0-z17}\[0]'
> +.*: Error: the register list must have a stride of 1 at operand 1 -- `luti6 {z0.h,z4.h,z8.h,z12.h},{z0.h,z1.h},{z0-z3}\[0]'
This error messsage is wrong, but I think this is due to an existing limitation
in the error reporting so is fine in this patch.
> +.*: Error: expected index at operand 3 -- `luti6 {z0.h,z4.h,z8.h,z12.h},{z0.h,z1.h},{z0-z1}'
> +.*: Error: end of vector register list not found at operand 3 -- `luti6 {z0.h,z4.h,z8.h,z12.h},{z0.h,z1.h},{z0.h-z1.h}\[0]'
> +.*: Error: too many registers in vector register list at operand 3 -- `luti6 {z0.b-z3.b},zt0,{z0-z5}'
> +.*: Error: start register out of range at operand 3 -- `luti6 {z0.b-z3.b},zt0,{z8-z10}'
> +.*: Error: end of vector register list not found at operand 3 -- `luti6 {z28.b-z31.b},zt0,{z0.b-z2.b}'
> +.*: Error: unexpected characters following instruction at operand 3 -- `luti6 {z0.b-z3.b},zt0,{z0-z2}\[0]'
> +.*: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrn z0.b,{z0.h-z1.h},#-1'
> +.*: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrn z0.b,{z0.h-z1.h},#0'
> +.*: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrn z0.b,{z0.h-z1.h},#9'
...
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index 2fc69c27791..56d35868e94 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -1812,6 +1812,10 @@
> { \
> QLF3(S_H,S_S,NIL), \
> }
> +#define OP_SVE_BHU \
> +{ \
> + QLF3(S_B,S_H,NIL), \
> +}
> #define OP_SVE_HU \
> { \
> QLF2(S_H,NIL), \
> @@ -2119,6 +2123,11 @@
> QLF3(S_B,S_S,NIL), \
> QLF3(S_H,S_D,NIL), \
> }
> +#define OP_SVE_VVU_BH_HS \
> +{ \
> + QLF3(S_B,S_H,NIL), \
> + QLF3(S_H,S_S,NIL), \
> +}
> #define OP_SVE_VVU_HSD_BHS \
> { \
> QLF3(S_H,S_B,NIL), \
> @@ -3057,6 +3066,12 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_f8f32 =
> AARCH64_FEATURES (2, SME_MOP4, SME_F8F32);
> static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
> AARCH64_FEATURES (2, SME_MOP4, SME_I16I64);
> +static const aarch64_feature_set aarch64_feature_sve2p3 =
> + AARCH64_FEATURE (SVE2p3);
> +static const aarch64_feature_set aarch64_feature_sme2p3 =
> + AARCH64_FEATURE (SME2p3);
> +static const aarch64_feature_set aarch64_feature_sve2p3_sme2p3 =
> + AARCH64_FEATURE (SVE2p3_SME2p3);
>
> #define CORE &aarch64_feature_v8
> #define FP &aarch64_feature_fp
> @@ -3181,6 +3196,9 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
> #define SME_MOP4_F8F16 &aarch64_feature_sme_mop4_f8f16
> #define SME_MOP4_F8F32 &aarch64_feature_sme_mop4_f8f32
> #define SME_MOP4_I16I64 &aarch64_feature_sme_mop4_i16i64
> +#define SVE2p3 &aarch64_feature_sve2p3
> +#define SME2p3 &aarch64_feature_sme2p3
> +#define SVE2p3_SME2p3 &aarch64_feature_sve2p3_sme2p3
>
> #define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
> { NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
> @@ -3510,6 +3528,16 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
> #define SME_MOP4_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
> { NAME, OPCODE, MASK, CLASS, 0, SME_MOP4_I16I64, OPS, QUALS, \
> FLAGS | F_STRICT, 0, TIED, NULL }
> +#define SVE2p3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS, TIED) \
> + { NAME, OPCODE, MASK, CLASS, OP, SVE2p3, OPS, QUALS, \
> + F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
> +#define SME2p3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS, TIED) \
> + { NAME, OPCODE, MASK, CLASS, OP, SME2p3, OPS, QUALS, \
> + FLAGS, CONSTRAINTS, TIED, NULL }
> +#define SVE2p3_SME2p3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS, TIED) \
> + { NAME, OPCODE, MASK, CLASS, OP, SVE2p3_SME2p3, OPS, QUALS, \
> + F_STRICT | F_INVALID_IMM_SYMS_3 | FLAGS, CONSTRAINTS, TIED, NULL }
> +
>
> #define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
> MOPS_INSN (NAME, OPCODE, MASK, 0, \
> @@ -7738,6 +7766,40 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> SME_MOP4_I16I64_INSN ("usmop4s", 0xa1c00218, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Znx2_6_3, SME_Zm_17_3), OP_SVE_DHH, 0, 0),
> SME_MOP4_I16I64_INSN ("usmop4s", 0xa1d00218, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Znx2_6_3, SME_Zmx2_17_3), OP_SVE_DHH, 0, 0),
>
> + /* SVE2p3 instructions. */
> + SVE2p3_INSN ("luti6", 0x4520ac00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_BBU, F_OD(2), 0, 0),
> +
> + /* SME2p3 instructions. */
> + SME2p3_INSN ("luti6", 0xc120f400, 0xffa0fc03, sve_misc, 0, OP3 (SME_Zdnx4, SVE_ZnxN, SME_Zmx2_INDEX_22), OP_SVE_HHU, F_OD(2), 0, 0),
> + SME2p3_INSN ("luti6", 0xc120fc00, 0xffa0fc0c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SVE_ZnxN, SME_Zmx2_INDEX_22), OP_SVE_HHU, F_OD(2), 0, 0),
> + SME2p3_INSN ("luti6", 0xc08a0000, 0xfffffc63, sve_misc, 0, OP3 (SME_Zdnx4, SME_ZT0, SME_Zn7xN_UNTYPED), OP_SVE_BUU, F_OD(3), 0, 0),
> + SME2p3_INSN ("luti6", 0xc09a0000, 0xfffffc6c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_ZT0, SME_Zn7xN_UNTYPED), OP_SVE_BUU, F_OD(3), 0, 0),
> + SME2p3_INSN ("luti6", 0xc0c84000, 0xfffffc00, sve_misc, 0, OP3 (SVE_Zd, SME_ZT0, SVE_Zn), OP_SVE_BUU, 0, 0, 0),
> +
> + /* SME2p3 / SME2p3 instructions. */
> + SVE2p3_SME2p3_INSN ("addqp", 0x04207800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("addsubp", 0x04207c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("sabal", 0x4400d400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
> + SVE2p3_SME2p3_INSN ("scvtf", 0x650c3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("scvtflt", 0x650c3800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("sdot", 0x44400000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
> + SVE2p3_SME2p3_INSN ("sdot", 0x44200000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
> + SVE2p3_SME2p3_INSN ("subp", 0x4410a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
> + SVE2p3_SME2p3_INSN ("uabal", 0x4400dc00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
> + SVE2p3_SME2p3_INSN ("ucvtf", 0x650c3400, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("ucvtflt", 0x650c3c00, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("udot", 0x44400400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
> + SVE2p3_SME2p3_INSN ("udot", 0x44200400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
> + SVE2p3_SME2p3_INSN ("fcvtzsn", 0x650d3000, 0xff3ffc20, sve_size_hsd, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_VV_BHS_HSD, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("fcvtzun", 0x650d3400, 0xff3ffc20, sve_size_hsd, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_VV_BHS_HSD, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("luti6", 0x4560ac00, 0xff60fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm1_23_INDEX), OP_SVE_HHU, F_OD(2), 0, 0),
> + SVE2p3_SME2p3_INSN ("sqrshrn", 0x45a82800, 0xfff8fc20, sve_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM3), OP_SVE_BHU, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("sqrshrun", 0x45a80800, 0xfff8fc20, sve_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM3), OP_SVE_BHU, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("sqshrn", 0x45a00000, 0xffe0fc20, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SME_Znx2, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BH_HS, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("sqshrun", 0x45a02000, 0xffe0fc20, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SME_Znx2, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BH_HS, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("uqrshrn", 0x45a83800, 0xfff8fc20, sve_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM3), OP_SVE_BHU, 0, 0, 0),
> + SVE2p3_SME2p3_INSN ("uqshrn", 0x45a01000, 0xffe0fc20, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SME_Znx2, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BH_HS, 0, 0, 0),
> +
> {0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
> };
>
> @@ -8305,6 +8367,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2_17_3", \
> 2 << OPD_F_OD_LSB, F(FLD_CONST_1, FLD_SME_Zm17_3, FLD_CONST_0), \
> "a list of SVE vector registers") \
> + Y(SVE_REGLIST, sve_reglist_index, "SME_Zmx2_INDEX_22", 2 << OPD_F_OD_LSB, \
> + F(FLD_SVE_Zm_16, FLD_imm1_22), "a list of SVE vector registers with index") \
> Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \
> F(FLD_SME_Zm2, FLD_CONST_0), "a list of SVE vector registers") \
> Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx4", 4 << OPD_F_OD_LSB, \
> @@ -8316,6 +8380,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> "a list of SVE vector registers") \
> Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \
> F(FLD_SME_Zn4, FLD_CONST_00), "a list of SVE vector registers") \
> + Y(SVE_REGLIST, sve_reglist, "SME_Zn7xN_UNTYPED", 3 << OPD_F_OD_LSB, \
This no longer requires operand-specific data, so I've set that field to 0.
Thanks,
Alice
> + F(FLD_SME_Zn4), "a list of untyped SVE vector registers") \
> Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx2_STRIDED", \
> 2 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt3), \
> "a list of SVE vector registers") \
> @@ -8384,6 +8450,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
> Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \
> F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \
> "Source scalable predicate register with index ") \
> + Y(IMMEDIATE, plain_shrimm, "SME_SHRIMM3", 0, F(FLD_SVE_imm3), \
> + "a shift-right immediate operand") \
> Y(IMMEDIATE, plain_shrimm, "SME_SHRIMM4", 0, F(FLD_SVE_imm4), \
> "a shift-right immediate operand") \
> Y(IMMEDIATE, sve_shrimm, "SME_SHRIMM5", 1 << OPD_F_OD_LSB, \
> --
> 2.43.0
>
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