[PATCH] aarch64: Update parse_vector_reg_list comment

[Alice Carlotti]

The information about indexes was wrong.  I've also adjusted the
formatting and improved other parts of the comment.

I intend to push this later today.


diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0ca54c3bd40bc87c8927c9e6f1ed1fb71e2ed289..1a8a5384c09ad4a3ec0197724841e52c5cd96547 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -1389,19 +1389,15 @@ reg_type_mask (aarch64_reg_type reg_type)
 
    It returns PARSE_FAIL if the register list is invalid.
 
-   If HAS_QUALIFIER is true, the registers in the list must have qualifiers
-   or the list is invalid.
-   If HAS_QUALIFIER is false, the registers in the list must not have
-   qualifiers or the list is invalid.
-
-   The list contains one to four registers.
-   Each register can be one of:
-   <Vt>.<T>[<index>]
-   <Vt>.<T>
-   All <T> should be identical.
-   All <index> should be identical.
-   There are restrictions on <Vt> numbers which are checked later
-   (by reg_list_valid_p).  */
+   If HAS_QUALIFIER is true, the registers must have type suffixes.
+   Otherwise, the registers must not have type suffixes.
+
+   If the register list contains typed SIMD registers without an element count
+   (e.g. "v0.h"), then the register list must be indexed.
+
+   The list must contain one to four registers, and all type suffixes must be
+   identical.  Restrictions on register numbers are checked later (by
+   reg_list_valid_p).  */
 
 static int
 parse_vector_reg_list (char **ccp, aarch64_reg_type type,