[PATCH v4 1/1] AArch64: Add FEAT_SVE2p3 and FEAT_SME2p3 instructions.
Sivan Shani
sivan.shani@arm.com
Wed Dec 10 17:26:36 GMT 2025
This patch includes:
- Flags for the FEAT_SVE2p3 and FEAT_SME2p3 features.
- Instructions:
- ADDQP
- ADDSUBP
- FCVTZSN
- FCVTZUN
- LUTI6 16-bit
- LUTI6 8-bit
- SABAL
- SCVTF
- SCVTFLT
- SDOT vectors
- SDOT indexed
- SQRSHRN
- SQRSHRUN
- SQSHRN
- SQSHRUN
- SUBP
- UABAL
- UCVTF
- UCVTFLT
- UDOT vectors
- UDOT indexed
- UQRSHRN
- UQSHRN
- LUTI6 vector
- LUTI6 table, four registers
- LUTI6 table, single, 8-bit
In addition, new operands:
- OPND_SME_ZmxN_INDEX_22: an operand represents a list of vector registers with an index.
- OPND_SME_Zn7x3_UNTYPED: an operand represents an untyped list of vector registers.
---
gas/config/tc-aarch64.c | 40 +-
gas/doc/c-aarch64.texi | 4 +
gas/testsuite/gas/aarch64/illegal-memtag.l | 2 +-
gas/testsuite/gas/aarch64/sme2p3-bad.d | 4 +
gas/testsuite/gas/aarch64/sme2p3-bad.l | 9 +
gas/testsuite/gas/aarch64/sme2p3-bad.s | 8 +
gas/testsuite/gas/aarch64/sme2p3.d | 33 ++
gas/testsuite/gas/aarch64/sme2p3.s | 25 +
gas/testsuite/gas/aarch64/sve-invalid.l | 8 +-
.../gas/aarch64/sve2-sme2-6-invalid.l | 16 +-
gas/testsuite/gas/aarch64/sve2p3.d | 246 ++++++++++
gas/testsuite/gas/aarch64/sve2p3.s | 238 +++++++++
include/opcode/aarch64.h | 9 +
opcodes/aarch64-asm-2.c | 4 +
opcodes/aarch64-asm.c | 15 +
opcodes/aarch64-asm.h | 1 +
opcodes/aarch64-dis-2.c | 454 ++++++++++++++----
opcodes/aarch64-dis.c | 19 +
opcodes/aarch64-dis.h | 1 +
opcodes/aarch64-opc-2.c | 3 +
opcodes/aarch64-opc.c | 12 +
opcodes/aarch64-opc.h | 1 +
opcodes/aarch64-tbl-2.h | 28 ++
opcodes/aarch64-tbl.h | 68 +++
24 files changed, 1135 insertions(+), 113 deletions(-)
create mode 100644 gas/testsuite/gas/aarch64/sme2p3-bad.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p3-bad.l
create mode 100644 gas/testsuite/gas/aarch64/sme2p3-bad.s
create mode 100644 gas/testsuite/gas/aarch64/sme2p3.d
create mode 100644 gas/testsuite/gas/aarch64/sme2p3.s
create mode 100644 gas/testsuite/gas/aarch64/sve2p3.d
create mode 100644 gas/testsuite/gas/aarch64/sve2p3.s
diff --git a/gas/config/tc-aarch64.c b/gas/config/tc-aarch64.c
index 0ca54c3bd40..ec683e1650d 100644
--- a/gas/config/tc-aarch64.c
+++ b/gas/config/tc-aarch64.c
@@ -1406,7 +1406,7 @@ reg_type_mask (aarch64_reg_type reg_type)
static int
parse_vector_reg_list (char **ccp, aarch64_reg_type type,
struct vector_type_el *vectype,
- bool has_qualifier)
+ bool has_qualifier, bool has_index)
{
char *str = *ccp;
int nb_regs;
@@ -1415,7 +1415,7 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
int in_range;
int ret_val;
bool error = false;
- bool expect_index = false;
+ bool expect_index = has_index;
unsigned int ptr_flags = PTR_IN_REGLIST;
if (*str != '{')
@@ -1451,6 +1451,8 @@ parse_vector_reg_list (char **ccp, aarch64_reg_type type,
{
reg = parse_reg (&str);
typeinfo.defined = 0;
+ if (has_index)
+ typeinfo.defined = NTA_HASINDEX;
}
if (!reg)
{
@@ -7023,9 +7025,10 @@ parse_operands (char *str, const aarch64_opcode *opcode)
break;
case AARCH64_OPND_SME_Znx2_BIT_INDEX:
+ case AARCH64_OPND_SME_Zn7x3_UNTYPED:
// A vector register list encoding a bit index.
reg_type = REG_TYPE_Z;
- val = parse_vector_reg_list (&str, reg_type, &vectype, false);
+ val = parse_vector_reg_list (&str, reg_type, &vectype, false, false);
if (val == PARSE_FAIL)
goto failure;
@@ -7045,6 +7048,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SME_Zmx2_17_3:
case AARCH64_OPND_SME_Zmx2:
case AARCH64_OPND_SME_Zmx4:
+ case AARCH64_OPND_SME_ZmxN_INDEX_22:
case AARCH64_OPND_SME_Znx2:
case AARCH64_OPND_SME_Znx4:
case AARCH64_OPND_SME_Ztx2_STRIDED:
@@ -7077,7 +7081,11 @@ parse_operands (char *str, const aarch64_opcode *opcode)
}
else
{
- val = parse_vector_reg_list (&str, reg_type, &vectype, true);
+ if (operands[i] == AARCH64_OPND_SME_ZmxN_INDEX_22)
+ val = parse_vector_reg_list (&str, reg_type, &vectype, false, true);
+ else
+ val = parse_vector_reg_list (&str, reg_type, &vectype, true, false);
+
if (val == PARSE_FAIL)
goto failure;
@@ -7087,14 +7095,14 @@ parse_operands (char *str, const aarch64_opcode *opcode)
goto failure;
}
- if ((int) vectype.width > 0 && *str != ',')
+ if (operands[i] != AARCH64_OPND_SME_ZmxN_INDEX_22 && (int) vectype.width > 0 && *str != ',')
{
set_fatal_syntax_error
(_("expected element type rather than vector type"));
goto failure;
}
}
- if (operands[i] == AARCH64_OPND_LEt)
+ if (operands[i] == AARCH64_OPND_LEt || operands[i] == AARCH64_OPND_SME_ZmxN_INDEX_22)
{
if (!(vectype.defined & NTA_HASINDEX))
goto failure;
@@ -7106,12 +7114,17 @@ parse_operands (char *str, const aarch64_opcode *opcode)
if (vectype.defined & NTA_HASINDEX)
goto failure;
if (!(vectype.defined & NTA_HASTYPE))
- {
- if (reg_type == REG_TYPE_Z || reg_type == REG_TYPE_P)
- set_fatal_syntax_error (_("missing type suffix"));
- goto failure;
- }
+ {
+ if (reg_type == REG_TYPE_Z || reg_type == REG_TYPE_P)
+ set_fatal_syntax_error (_("missing type suffix"));
+ goto failure;
+ }
}
+ if (operands[i] == AARCH64_OPND_SME_ZmxN_INDEX_22) {
+ info->qualifier = AARCH64_OPND_QLF_NIL;
+ break;
+ }
+
info->qualifier = vectype_to_qualifier (&vectype);
if (info->qualifier == AARCH64_OPND_QLF_NIL)
goto failure;
@@ -7175,6 +7188,7 @@ parse_operands (char *str, const aarch64_opcode *opcode)
case AARCH64_OPND_SVE_SHLIMM_PRED:
case AARCH64_OPND_SVE_SHLIMM_UNPRED:
case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
+ case AARCH64_OPND_SME_SHRIMM3:
case AARCH64_OPND_SME_SHRIMM4:
case AARCH64_OPND_SME_SHRIMM5:
case AARCH64_OPND_SVE_SHRIMM_PRED:
@@ -10905,6 +10919,8 @@ static const struct aarch64_option_cpu_value_table aarch64_features[] = {
{"ssve-fexpa", AARCH64_FEATURE (SSVE_FEXPA), AARCH64_FEATURE (SME2)},
{"sme-tmop", AARCH64_FEATURE (SME_TMOP), AARCH64_FEATURE (SME2)},
{"sme-mop4", AARCH64_FEATURE (SME_MOP4), AARCH64_FEATURE (SME2)},
+ {"sve2p3", AARCH64_FEATURE (SVE2p3), AARCH64_FEATURE (SVE2p2)},
+ {"sme2p3", AARCH64_FEATURE (SME2p3), AARCH64_FEATURES (2, SME2p2, SME_LUTv2)},
{NULL, AARCH64_NO_FEATURES, AARCH64_NO_FEATURES},
};
@@ -10938,6 +10954,8 @@ static const struct aarch64_virtual_dependency_table aarch64_dependencies[] = {
{AARCH64_FEATURE (SME2p1), AARCH64_FEATURE (SVE2p1_SME2p1)},
{AARCH64_FEATURE (SVE2p2), AARCH64_FEATURE (SVE2p2_SME2p2)},
{AARCH64_FEATURE (SME2p2), AARCH64_FEATURES (2, SVE_SME2p2, SVE2p2_SME2p2)},
+ {AARCH64_FEATURE (SVE2p3), AARCH64_FEATURE (SVE2p3_SME2p3)},
+ {AARCH64_FEATURE (SME2p3), AARCH64_FEATURE (SVE2p3_SME2p3)},
};
static aarch64_feature_set
diff --git a/gas/doc/c-aarch64.texi b/gas/doc/c-aarch64.texi
index 9683d411ce9..bf9abbc478f 100644
--- a/gas/doc/c-aarch64.texi
+++ b/gas/doc/c-aarch64.texi
@@ -319,6 +319,8 @@ automatically cause those extensions to be disabled.
@tab Enable SME2.1.
@item @code{sme2p2} @tab @code{sme2p1}
@tab Enable SME2.2.
+@item @code{sme2p3} @tab @code{sme2p2}
+ @tab Enable SME2.3.
@item @code{ssbs} @tab
@tab Enable Speculative Store Bypassing Safe state read and write.
@item @code{ssve-aes} @tab @code{sme2}, @code{sve-aes}
@@ -361,6 +363,8 @@ automatically cause those extensions to be disabled.
@tab Enable SVE2.1.
@item @code{sve2p2} @tab @code{sve2p1}
@tab Enable SVE2.2.
+@item @code{sve2p3} @tab @code{sve2p2}
+ @tab Enable SVE2.3.
@item @code{the} @tab
@tab Enable the Translation Hardening Extension.
@item @code{tme} @tab
diff --git a/gas/testsuite/gas/aarch64/illegal-memtag.l b/gas/testsuite/gas/aarch64/illegal-memtag.l
index 476c345d366..9e9d6bf0dae 100644
--- a/gas/testsuite/gas/aarch64/illegal-memtag.l
+++ b/gas/testsuite/gas/aarch64/illegal-memtag.l
@@ -26,7 +26,7 @@
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `gmi x1,xzr,x3'
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 1 -- `addg xzr,x2,#0,#0'
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subg x1,xzr,#0,#0'
-[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `subp sp,x1,x2'
+[^:]*:[0-9]+: Error: expected an integer register or SVE vector register at operand 1 -- `subp sp,x1,x2'
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 2 -- `subp x1,xzr,x2'
[^:]*:[0-9]+: Error: expected an integer or stack pointer register at operand 3 -- `subp x1,x2,xzr'
[^:]*:[0-9]+: Error: expected an integer or zero register at operand 1 -- `subps sp,x1,x2'
diff --git a/gas/testsuite/gas/aarch64/sme2p3-bad.d b/gas/testsuite/gas/aarch64/sme2p3-bad.d
new file mode 100644
index 00000000000..f65e16eb369
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p3-bad.d
@@ -0,0 +1,4 @@
+#name: Negative test for the SME_ZmxN_INDEX_22, SME_Zn7x3_UNTYPED, SME_SHRIMM3 opernads
+#as: -march=armv8-a+sme2p3
+#source: sme2p3-bad.s
+#error_output: sme2p3-bad.l
diff --git a/gas/testsuite/gas/aarch64/sme2p3-bad.l b/gas/testsuite/gas/aarch64/sme2p3-bad.l
new file mode 100644
index 00000000000..03d7431fead
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p3-bad.l
@@ -0,0 +1,9 @@
+.*: Assembler messages:
+.*: Error: expected index at operand 3 -- `luti6 {z0.h-z3.h},{z0.h-z1.h},{z0-z1}'
+.*: Error: too many registers in vector register list at operand 3 -- `luti6 {z0.h-z3.h},{z0.h-z1.h},{z0-z17}\[0]'
+.*: Error: expected index at operand 3 -- `luti6 {z0.h,z4.h,z8.h,z12.h},{z0.h,z1.h},{z0-z1}'
+.*: Error: too many registers in vector register list at operand 3 -- `luti6 {z0.b-z3.b},zt0,{z0-z5}'
+.*: Error: end of vector register list not found at operand 3 -- `luti6 {z28.b-z31.b},zt0,{z0.b-z2.b}'
+.*: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrn z0.b,{z0.h-z1.h},#-1'
+.*: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrn z0.b,{z0.h-z1.h},#0'
+.*: Error: immediate value out of range 1 to 8 at operand 3 -- `sqrshrn z0.b,{z0.h-z1.h},#9'
diff --git a/gas/testsuite/gas/aarch64/sme2p3-bad.s b/gas/testsuite/gas/aarch64/sme2p3-bad.s
new file mode 100644
index 00000000000..2440d7e1748
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p3-bad.s
@@ -0,0 +1,8 @@
+luti6 { z0.h-z3.h }, { z0.h-z1.h }, { z0-z1 }
+luti6 {z0.h-z3.h},{z0.h-z1.h},{z0-z17}[0]
+luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0-z1 }
+luti6 { z0.b-z3.b }, zt0, { z0-z5 }
+luti6 { z28.b-z31.b }, zt0, { z0.b-z2.b }
+sqrshrn z0.b, { z0.h-z1.h }, #-1
+sqrshrn z0.b, { z0.h-z1.h }, #0
+sqrshrn z0.b, { z0.h-z1.h }, #9
diff --git a/gas/testsuite/gas/aarch64/sme2p3.d b/gas/testsuite/gas/aarch64/sme2p3.d
new file mode 100644
index 00000000000..a53dd1ab9e3
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p3.d
@@ -0,0 +1,33 @@
+#as: -march=armv8-a+sme2p3
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <\.text>:
+ *[0-9a-f]+: c08a0000 luti6 {z0.b-z3.b}, zt0, {z0-z2}
+ *[0-9a-f]+: c08a001c luti6 {z28.b-z31.b}, zt0, {z0-z2}
+ *[0-9a-f]+: c08a0380 luti6 {z0.b-z3.b}, zt0, {z7-z9}
+ *[0-9a-f]+: c09a0000 luti6 {z0.b, z4.b, z8.b, z12.b}, zt0, {z0-z2}
+ *[0-9a-f]+: c09a0013 luti6 {z19.b, z23.b, z27.b, z31.b}, zt0, {z0-z2}
+ *[0-9a-f]+: c09a0380 luti6 {z0.b, z4.b, z8.b, z12.b}, zt0, {z7-z9}
+ *[0-9a-f]+: c0c84000 luti6 z0.b, zt0, z0
+ *[0-9a-f]+: c0c8401f luti6 z31.b, zt0, z0
+ *[0-9a-f]+: c0c843e0 luti6 z0.b, zt0, z31
+
+ *[0-9a-f]+: c120f400 luti6 {z0.h-z3.h}, {z0.h-z1.h}, {z0-z1}\[0\]
+ *[0-9a-f]+: c120f41c luti6 {z28.h-z31.h}, {z0.h-z1.h}, {z0-z1}\[0\]
+ *[0-9a-f]+: c120f7c0 luti6 {z0.h-z3.h}, {z30.h-z31.h}, {z0-z1}\[0\]
+ *[0-9a-f]+: c120f7e0 luti6 {z0.h-z3.h}, {z31.h-z0.h}, {z0-z1}\[0\]
+ *[0-9a-f]+: c13ef400 luti6 {z0.h-z3.h}, {z0.h-z1.h}, {z30-z31}\[0\]
+ *[0-9a-f]+: c13ff400 luti6 {z0.h-z3.h}, {z0.h-z1.h}, {z31-z0}\[0\]
+ *[0-9a-f]+: c160f400 luti6 {z0.h-z3.h}, {z0.h-z1.h}, {z0-z1}\[1\]
+
+ *[0-9a-f]+: c120fc00 luti6 {z0.h, z4.h, z8.h, z12.h}, {z0.h-z1.h}, {z0-z1}\[0\]
+ *[0-9a-f]+: c120fc13 luti6 {z19\.h, z23\.h, z27\.h, z31\.h}, {z0\.h-z1\.h}, {z0-z1}\[0\]
+ *[0-9a-f]+: c120ffc0 luti6 {z0\.h, z4\.h, z8\.h, z12\.h}, {z30\.h-z31\.h}, {z0-z1}\[0\]
+ *[0-9a-f]+: c120ffe0 luti6 {z0\.h, z4\.h, z8\.h, z12\.h}, {z31\.h-z0\.h}, {z0-z1}\[0\]
+ *[0-9a-f]+: c13efc00 luti6 {z0\.h, z4\.h, z8\.h, z12\.h}, {z0\.h-z1\.h}, {z30-z31}\[0\]
+ *[0-9a-f]+: c13ffc00 luti6 {z0\.h, z4\.h, z8\.h, z12\.h}, {z0\.h-z1\.h}, {z31-z0}\[0\]
+ *[0-9a-f]+: c160fc00 luti6 {z0\.h, z4\.h, z8\.h, z12\.h}, {z0\.h-z1\.h}, {z0-z1}\[1\]
diff --git a/gas/testsuite/gas/aarch64/sme2p3.s b/gas/testsuite/gas/aarch64/sme2p3.s
new file mode 100644
index 00000000000..253c7a881c1
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sme2p3.s
@@ -0,0 +1,25 @@
+luti6 { z0.b-z3.b }, zt0, { z0-z2 }
+luti6 { z28.b-z31.b }, zt0, { z0-z2 }
+luti6 { z0.b-z3.b }, zt0, { z7-z9 }
+luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z0-z2 }
+luti6 { z19.b, z23.b, z27.b, z31.b }, zt0, { z0-z2 }
+luti6 { z0.b, z4.b, z8.b, z12.b }, zt0, { z7-z9 }
+luti6 z0.b, zt0, z0
+luti6 z31.b, zt0, z0
+luti6 z0.b, zt0, z31
+
+luti6 { z0.h-z3.h }, { z0.h-z1.h }, { z0-z1 }[0]
+luti6 { z28.h-z31.h }, { z0.h-z1.h }, { z0-z1 }[0]
+luti6 { z0.h-z3.h }, { z30.h-z31.h }, { z0-z1 }[0]
+luti6 { z0.h-z3.h }, { z31.h-z0.h }, { z0-z1 }[0]
+luti6 { z0.h-z3.h }, { z0.h-z1.h }, { z30-z31 }[0]
+luti6 { z0.h-z3.h }, { z0.h-z1.h }, { z31-z0 }[0]
+luti6 { z0.h-z3.h }, { z0.h-z1.h }, { z0-z1 }[1]
+
+luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0-z1 }[0]
+luti6 { z19.h, z23.h, z27.h, z31.h }, { z0.h, z1.h }, { z0-z1 }[0]
+luti6 { z0.h, z4.h, z8.h, z12.h }, { z30.h, z31.h }, { z0-z1 }[0]
+luti6 { z0.h, z4.h, z8.h, z12.h }, { z31.h, z0.h }, { z0-z1 }[0]
+luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z30-z31 }[0]
+luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z31-z0 }[0]
+luti6 { z0.h, z4.h, z8.h, z12.h }, { z0.h, z1.h }, { z0-z1 }[1]
diff --git a/gas/testsuite/gas/aarch64/sve-invalid.l b/gas/testsuite/gas/aarch64/sve-invalid.l
index 6b5f38f3d0f..1e54e43d14b 100644
--- a/gas/testsuite/gas/aarch64/sve-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve-invalid.l
@@ -1150,9 +1150,7 @@
.*: Error: invalid addressing mode at operand 3 -- `ld1rqd {z0\.d},p0/z,\[x0,x1,lsl ?#2\]'
.*: Error: operand mismatch -- `sdot z0\.b,z1\.b,z2\.b'
.*: Info: did you mean this\?
-.*: Info: sdot z0\.s, z1\.b, z2\.b
-.*: Info: other valid variant\(s\):
-.*: Info: sdot z0\.d, z1\.h, z2\.h
+.*: Info: sdot z0\.h, z1\.b, z2\.b
.*: Error: operand mismatch -- `sdot z0\.h,z1\.h,z2\.h'
.*: Info: did you mean this\?
.*: Info: sdot z0\.s, z1\.h, z2\.h
@@ -1178,9 +1176,7 @@
.*: Info: sdot z0\.d, z1\.h, z2\.h\[0\]
.*: Error: operand mismatch -- `udot z0\.b,z1\.b,z2\.b'
.*: Info: did you mean this\?
-.*: Info: udot z0\.s, z1\.b, z2\.b
-.*: Info: other valid variant\(s\):
-.*: Info: udot z0\.d, z1\.h, z2\.h
+.*: Info: udot z0\.h, z1\.b, z2\.b
.*: Error: operand mismatch -- `udot z0\.h,z1\.h,z2\.h'
.*: Info: did you mean this\?
.*: Info: udot z0\.s, z1\.h, z2\.h
diff --git a/gas/testsuite/gas/aarch64/sve2-sme2-6-invalid.l b/gas/testsuite/gas/aarch64/sve2-sme2-6-invalid.l
index 7792afa90ea..1b79ca8211f 100644
--- a/gas/testsuite/gas/aarch64/sve2-sme2-6-invalid.l
+++ b/gas/testsuite/gas/aarch64/sve2-sme2-6-invalid.l
@@ -7,14 +7,10 @@
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrn z0\.h,{ ?z0\.s ?- ?z1\.s ?},#0'
[^ :]+:[0-9]+: Error: immediate value out of range 1 to 16 at operand 3 -- `sqrshrn z0\.h,{ ?z0\.s ?- ?z1\.s ?},#17'
[^ :]+:[0-9]+: Error: immediate operand required at operand 3 -- `sqrshrn z0\.h,{ ?z0\.s ?- ?z1\.s ?},x0'
-[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrn z0\.b,{ ?z0\.h ?- ?z1\.h ?},#1'
-[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrshrn z0\.b, {z0\.s-z1\.s}, #1
-[^ :]+:[0-9]+: Info: other valid variant\(s\):
-[^ :]+:[0-9]+: Info: sqrshrn z0\.h, {z0\.d-z1\.d}, #1
-[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrn z0\.s,{ ?z0\.d ?- ?z1\.d ?},#1'
-[^ :]+:[0-9]+: Info: did you mean this\?
-[^ :]+:[0-9]+: Info: sqrshrn z0\.h, {z0\.d-z1\.d}, #1
-[^ :]+:[0-9]+: Info: other valid variant\(s\):
-[^ :]+:[0-9]+: Info: sqrshrn z0\.b, {z0\.s-z1\.s}, #1
+[^ :]+:[0-9]+: Error: selected processor does not support `sqrshrn z0\.b,{ ?z0\.h ?- ?z1\.h ?},#1'
+[^ :]+:[0-9]+: Error: operand mismatch -- `sqrshrn z0\.s,{ ?z0\.d- ?z1\.d},#1'
+[^ :]+:[0-9]+: Info:\s+did you mean this\?
+[^ :]+:[0-9]+: Info:\s+sqrshrn z0\.h, { ?z0\.d- ?z1\.d}, #1
+[^ :]+:[0-9]+: Info:\s+other valid variant\(s\):
+[^ :]+:[0-9]+: Info:\s+sqrshrn z0\.b, { ?z0\.s ?- ?z1\.s ?}, #1
[^ :]+:[0-9]+: Warning: SVE `movprfx' compatible instruction expected -- `sqrshrn z0\.h,{ ?z2\.s ?- ?z3\.s ?},#1'
diff --git a/gas/testsuite/gas/aarch64/sve2p3.d b/gas/testsuite/gas/aarch64/sve2p3.d
new file mode 100644
index 00000000000..5a327b11e49
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p3.d
@@ -0,0 +1,246 @@
+#as: -march=armv8-a+sve2p3
+#as: -march=armv8-a+sme2p3
+#objdump: -dr
+
+.*: file format .*
+
+Disassembly of section \.text:
+
+0+ <\.text>:
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+ *[0-9a-f]+: 04607800 addqp z0\.h, z0\.h, z0\.h
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+ *[0-9a-f]+: 04ff7800 addqp z0\.d, z0\.d, z31\.d
+
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+ *[0-9a-f]+: 04607c00 addsubp z0\.h, z0\.h, z0\.h
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+ *[0-9a-f]+: 04ff7c00 addsubp z0\.d, z0\.d, z31\.d
+
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+ *[0-9a-f]+: 65cd33c0 fcvtzsn z0\.s, {z30\.d-z31\.d}
+
+ *[0-9a-f]+: 654d3400 fcvtzun z0\.b, {z0\.h-z1\.h}
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+ *[0-9a-f]+: 658d3400 fcvtzun z0\.h, {z0\.s-z1\.s}
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+ *[0-9a-f]+: 65cd3400 fcvtzun z0\.s, {z0\.d-z1\.d}
+ *[0-9a-f]+: 65cd341f fcvtzun z31\.s, {z0\.d-z1\.d}
+ *[0-9a-f]+: 65cd37c0 fcvtzun z0\.s, {z30\.d-z31\.d}
+
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+ *[0-9a-f]+: 45e0ac00 luti6 z0.h, {z0.h-z1.h}, z0\[1\]
+
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+
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+ *[0-9a-f]+: 44380000 sdot z0\.h, z0\.b, z0\.b\[3\]
+ *[0-9a-f]+: 44780000 sdot z0\.h, z0\.b, z0\.b\[7\]
+
+ *[0-9a-f]+:[ \t]+45a82800[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#8
+ *[0-9a-f]+:[ \t]+45a8281f[ \t]+sqrshrn[ \t]+z31\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#8
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+ *[0-9a-f]+:[ \t]+45af2800[ \t]+sqrshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#1
+
+ *[0-9a-f]+:[ \t]+45a80800[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#8
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+ *[0-9a-f]+:[ \t]+45af0800[ \t]+sqrshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#1
+
+ *[0-9a-f]+:[ \t]+45a80000[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#8
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+ *[0-9a-f]+:[ \t]+45af0000[ \t]+sqshrn[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#1
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+ *[0-9a-f]+:[ \t]+45bb0000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#5
+ *[0-9a-f]+:[ \t]+45bf0000[ \t]+sqshrn[ \t]+z0\.h,[ \t]+{z0\.s-z1\.s},[ \t]+#1
+
+ *[0-9a-f]+:[ \t]+45a82000[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#8
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+ *[0-9a-f]+:[ \t]+45ab2000[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#5
+ *[0-9a-f]+:[ \t]+45af2000[ \t]+sqshrun[ \t]+z0\.b,[ \t]+{z0\.h-z1\.h},[ \t]+#1
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+ *[0-9a-f]+: 442007e0 udot z0\.h, z31\.b, z0\.b\[0\]
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+ *[0-9a-f]+: 4488cc00 udot z0\.s, z0\.h, z0\.h\[1\]
+ *[0-9a-f]+: 4498cc00 udot z0\.s, z0\.h, z0\.h\[3\]
+
+ *[0-9a-f]+: 45a83800 uqrshrn z0\.b, {z0\.h-z1\.h}, #8
+ *[0-9a-f]+: 45a8381f uqrshrn z31\.b, {z0\.h-z1\.h}, #8
+ *[0-9a-f]+: 45a83bc0 uqrshrn z0\.b, {z30\.h-z31\.h}, #8
+ *[0-9a-f]+: 45ab3800 uqrshrn z0\.b, {z0\.h-z1\.h}, #5
+ *[0-9a-f]+: 45af3800 uqrshrn z0\.b, {z0\.h-z1\.h}, #1
+
+ *[0-9a-f]+: 45b03800 uqrshrn z0\.h, {z0.s-z1.s}, #16
+ *[0-9a-f]+: 45b0381f uqrshrn z31\.h, {z0.s-z1.s}, #16
+ *[0-9a-f]+: 45b03bc0 uqrshrn z0\.h, {z30.s-z31.s}, #16
+ *[0-9a-f]+: 45bb3800 uqrshrn z0\.h, {z0.s-z1.s}, #5
+ *[0-9a-f]+: 45bf3800 uqrshrn z0\.h, {z0.s-z1.s}, #1
+
+ *[0-9a-f]+: 45a81000 uqshrn z0\.b, {z0\.h-z1\.h}, #8
+ *[0-9a-f]+: 45a8101f uqshrn z31\.b, {z0\.h-z1\.h}, #8
+ *[0-9a-f]+: 45a813c0 uqshrn z0\.b, {z30\.h-z31\.h}, #8
+ *[0-9a-f]+: 45ab1000 uqshrn z0\.b, {z0\.h-z1\.h}, #5
+ *[0-9a-f]+: 45af1000 uqshrn z0\.b, {z0\.h-z1\.h}, #1
+
+ *[0-9a-f]+: 45b01000 uqshrn z0\.h, {z0.s-z1.s}, #16
+ *[0-9a-f]+: 45b0101f uqshrn z31\.h, {z0.s-z1.s}, #16
+ *[0-9a-f]+: 45b013c0 uqshrn z0\.h, {z30.s-z31.s}, #16
+ *[0-9a-f]+: 45bb1000 uqshrn z0\.h, {z0.s-z1.s}, #5
+ *[0-9a-f]+: 45bf1000 uqshrn z0\.h, {z0.s-z1.s}, #1
+
+ *[0-9a-f]+: 4520ac00 luti6 z0.b, {z0.b-z1.b}, z0
+ *[0-9a-f]+: 4520ac1f luti6 z31.b, {z0.b-z1.b}, z0
+ *[0-9a-f]+: 4520afe0 luti6 z0.b, {z31.b-z0.b}, z0
+ *[0-9a-f]+: 453fac00 luti6 z0.b, {z0.b-z1.b}, z31
diff --git a/gas/testsuite/gas/aarch64/sve2p3.s b/gas/testsuite/gas/aarch64/sve2p3.s
new file mode 100644
index 00000000000..01592db8c22
--- /dev/null
+++ b/gas/testsuite/gas/aarch64/sve2p3.s
@@ -0,0 +1,238 @@
+addqp z0.b, z0.b, z0.b
+addqp z31.b, z0.b, z0.b
+addqp z0.b, z31.b, z0.b
+addqp z0.b, z0.b, z31.b
+addqp z0.h, z0.h, z0.h
+addqp z31.h, z0.h, z0.h
+addqp z0.h, z31.h, z0.h
+addqp z0.h, z0.h, z31.h
+addqp z0.s, z0.s, z0.s
+addqp z31.s, z0.s, z0.s
+addqp z0.s, z31.s, z0.s
+addqp z0.s, z0.s, z31.s
+addqp z0.d, z0.d, z0.d
+addqp z31.d, z0.d, z0.d
+addqp z0.d, z31.d, z0.d
+addqp z0.d, z0.d, z31.d
+
+addsubp z0.b, z0.b, z0.b
+addsubp z31.b, z0.b, z0.b
+addsubp z0.b, z31.b, z0.b
+addsubp z0.b, z0.b, z31.b
+addsubp z0.h, z0.h, z0.h
+addsubp z31.h, z0.h, z0.h
+addsubp z0.h, z31.h, z0.h
+addsubp z0.h, z0.h, z31.h
+addsubp z0.s, z0.s, z0.s
+addsubp z31.s, z0.s, z0.s
+addsubp z0.s, z31.s, z0.s
+addsubp z0.s, z0.s, z31.s
+addsubp z0.d, z0.d, z0.d
+addsubp z31.d, z0.d, z0.d
+addsubp z0.d, z31.d, z0.d
+addsubp z0.d, z0.d, z31.d
+
+fcvtzsn z0.b, { z0.h-z1.h }
+fcvtzsn z31.b, { z0.h-z1.h }
+fcvtzsn z0.b, { z30.h-z31.h }
+fcvtzsn z0.h, { z0.s-z1.s }
+fcvtzsn z31.h, { z0.s-z1.s }
+fcvtzsn z0.h, { z30.s-z31.s }
+fcvtzsn z0.s, { z0.d-z1.d }
+fcvtzsn z31.s, { z0.d-z1.d }
+fcvtzsn z0.s, { z30.d-z31.d }
+
+fcvtzun z0.b, { z0.h-z1.h }
+fcvtzun z31.b, { z0.h-z1.h }
+fcvtzun z0.b, { z30.h-z31.h }
+fcvtzun z0.h, { z0.s-z1.s }
+fcvtzun z31.h, { z0.s-z1.s }
+fcvtzun z0.h, { z30.s-z31.s }
+fcvtzun z0.s, { z0.d-z1.d }
+fcvtzun z31.s, { z0.d-z1.d }
+fcvtzun z0.s, { z30.d-z31.d }
+
+luti6 z0.h, { z0.h, z1.h }, z0[0]
+luti6 z31.h, { z0.h, z1.h }, z0[0]
+luti6 z0.h, { z31.h, z0.h }, z0[0]
+luti6 z0.h, { z0.h, z1.h }, z31[0]
+luti6 z0.h, { z0.h, z1.h }, z0[1]
+
+sabal z0.h, z0.b, z0.b
+sabal z31.h, z0.b, z0.b
+sabal z0.h, z31.b, z0.b
+sabal z0.h, z0.b, z31.b
+sabal z0.s, z0.h, z0.h
+sabal z31.s, z0.h, z0.h
+sabal z0.s, z31.h, z0.h
+sabal z0.s, z0.h, z31.h
+sabal z0.d, z0.s, z0.s
+sabal z31.d, z0.s, z0.s
+sabal z0.d, z31.s, z0.s
+sabal z0.d, z0.s, z31.s
+
+scvtf z0.h, z0.b
+scvtf z31.h, z0.b
+scvtf z0.h, z31.b
+scvtf z0.s, z0.h
+scvtf z31.s, z0.h
+scvtf z0.s, z31.h
+scvtf z0.d, z0.s
+scvtf z31.d, z0.s
+scvtf z0.d, z31.s
+
+scvtflt z0.h, z0.b
+scvtflt z31.h, z0.b
+scvtflt z0.h, z31.b
+scvtflt z0.s, z0.h
+scvtflt z31.s, z0.h
+scvtflt z0.s, z31.h
+scvtflt z0.d, z0.s
+scvtflt z31.d, z0.s
+scvtflt z0.d, z31.s
+
+sdot z0.h, z0.b, z0.b
+sdot z31.h, z0.b, z0.b
+sdot z0.h, z31.b, z0.b
+sdot z0.h, z0.b, z31.b
+sdot z0.h, z0.b, z0.b[0]
+sdot z31.h, z0.b, z0.b[0]
+sdot z0.h, z31.b, z0.b[0]
+sdot z0.h, z0.b, z7.b[0]
+sdot z0.h, z0.b, z0.b[3]
+sdot z0.h, z0.b, z0.b[7]
+
+sqrshrn z0.b, { z0.h-z1.h }, #8
+sqrshrn z31.b, { z0.h-z1.h }, #8
+sqrshrn z0.b, { z30.h-z31.h }, #8
+sqrshrn z0.b, { z0.h-z1.h }, #5
+sqrshrn z0.b, { z0.h-z1.h }, #1
+
+sqrshrun z0.b, { z0.h-z1.h }, #8
+sqrshrun z31.b, { z0.h-z1.h }, #8
+sqrshrun z0.b, { z30.h-z31.h }, #8
+sqrshrun z0.b, { z0.h-z1.h }, #5
+sqrshrun z0.b, { z0.h-z1.h }, #1
+
+sqshrn z0.b, { z0.h-z1.h }, #8
+sqshrn z31.b, { z0.h-z1.h }, #8
+sqshrn z0.b, { z30.h-z31.h }, #8
+sqshrn z0.b, { z0.h-z1.h }, #5
+sqshrn z0.b, { z0.h-z1.h }, #1
+sqshrn z0.h, { z0.s-z1.s }, #16
+sqshrn z31.h, { z0.s-z1.s }, #16
+sqshrn z0.h, { z30.s-z31.s }, #16
+sqshrn z0.h, { z0.s-z1.s }, #5
+sqshrn z0.h, { z0.s-z1.s }, #1
+
+sqshrun z0.b, { z0.h-z1.h }, #8
+sqshrun z31.b, { z0.h-z1.h }, #8
+sqshrun z0.b, { z30.h-z31.h }, #8
+sqshrun z0.b, { z0.h-z1.h }, #5
+sqshrun z0.b, { z0.h-z1.h }, #1
+sqshrun z0.h, { z0.s-z1.s }, #16
+sqshrun z31.h, { z0.s-z1.s }, #16
+sqshrun z0.h, { z30.s-z31.s }, #16
+sqshrun z0.h, { z0.s-z1.s }, #5
+sqshrun z0.h, { z0.s-z1.s }, #1
+
+subp z0.b, p0/m, z0.b, z0.b
+subp z31.b, p0/m, z31.b, z0.b
+subp z0.b, p0/m, z0.b, z31.b
+subp z0.b, p7/m, z0.b, z0.b
+subp z0.h, p0/m, z0.h, z0.h
+subp z31.h, p0/m, z31.h, z0.h
+subp z0.h, p0/m, z0.h, z31.h
+subp z0.h, p7/m, z0.h, z0.h
+subp z0.s, p0/m, z0.s, z0.s
+subp z31.s, p0/m, z31.s, z0.s
+subp z0.s, p0/m, z0.s, z31.s
+subp z0.s, p7/m, z0.s, z0.s
+subp z0.d, p0/m, z0.d, z0.d
+subp z31.d, p0/m, z31.d, z0.d
+subp z0.d, p0/m, z0.d, z31.d
+subp z0.d, p7/m, z0.d, z0.d
+
+uabal z0.h, z0.b, z0.b
+uabal z31.h, z0.b, z0.b
+uabal z0.h, z31.b, z0.b
+uabal z0.h, z0.b, z31.b
+uabal z0.s, z0.h, z0.h
+uabal z31.s, z0.h, z0.h
+uabal z0.s, z31.h, z0.h
+uabal z0.s, z0.h, z31.h
+uabal z0.d, z0.s, z0.s
+uabal z31.d, z0.s, z0.s
+uabal z0.d, z31.s, z0.s
+uabal z0.d, z0.s, z31.s
+
+ucvtf z0.h, z0.b
+ucvtf z31.h, z0.b
+ucvtf z0.h, z31.b
+ucvtf z0.s, z0.h
+ucvtf z31.s, z0.h
+ucvtf z0.s, z31.h
+ucvtf z0.d, z0.s
+ucvtf z31.d, z0.s
+ucvtf z0.d, z31.s
+
+ucvtflt z0.h, z0.b
+ucvtflt z31.h, z0.b
+ucvtflt z0.h, z31.b
+ucvtflt z0.s, z0.h
+ucvtflt z31.s, z0.h
+ucvtflt z0.s, z31.h
+ucvtflt z0.d, z0.s
+ucvtflt z31.d, z0.s
+ucvtflt z0.d, z31.s
+
+udot z0.h, z0.b, z0.b
+udot z31.h, z0.b, z0.b
+udot z0.h, z31.b, z0.b
+udot z0.h, z0.b, z31.b
+udot z0.s, z0.h, z0.h
+udot z31.s, z0.h, z0.h
+udot z0.s, z31.h, z0.h
+udot z0.s, z0.h, z31.h
+udot z0.h, z0.b, z0.b[0]
+udot z31.h, z0.b, z0.b[0]
+udot z0.h, z31.b, z0.b[0]
+udot z0.h, z0.b, z7.b[0]
+udot z0.h, z0.b, z0.b[3]
+udot z0.h, z0.b, z0.b[7]
+udot z0.s, z0.h, z0.h[0]
+udot z31.s, z0.h, z0.h[0]
+udot z0.s, z31.h, z0.h[0]
+udot z0.s, z0.h, z7.h[0]
+udot z0.s, z0.h, z0.h[1]
+udot z0.s, z0.h, z0.h[3]
+
+uqrshrn z0.b, { z0.h-z1.h }, #8
+uqrshrn z31.b, { z0.h-z1.h }, #8
+uqrshrn z0.b, { z30.h-z31.h }, #8
+uqrshrn z0.b, { z0.h-z1.h }, #5
+uqrshrn z0.b, { z0.h-z1.h }, #1
+
+uqrshrn z0.h, { z0.s-z1.s }, #16
+uqrshrn z31.h, { z0.s-z1.s }, #16
+uqrshrn z0.h, { z30.s-z31.s }, #16
+uqrshrn z0.h, { z0.s-z1.s }, #5
+uqrshrn z0.h, { z0.s-z1.s }, #1
+
+uqshrn z0.b, { z0.h-z1.h }, #8
+uqshrn z31.b, { z0.h-z1.h }, #8
+uqshrn z0.b, { z30.h-z31.h }, #8
+uqshrn z0.b, { z0.h-z1.h }, #5
+uqshrn z0.b, { z0.h-z1.h }, #1
+
+uqshrn z0.h, { z0.s-z1.s }, #16
+uqshrn z31.h, { z0.s-z1.s }, #16
+uqshrn z0.h, { z30.s-z31.s }, #16
+uqshrn z0.h, { z0.s-z1.s }, #5
+uqshrn z0.h, { z0.s-z1.s }, #1
+
+.arch armv8-a+sve2p3
+luti6 z0.b, { z0.b, z1.b }, z0
+luti6 z31.b, { z0.b, z1.b }, z0
+luti6 z0.b, { z31.b, z0.b }, z0
+luti6 z0.b, { z0.b, z1.b }, z31
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index e65b61c3f9c..08478a24aea 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -263,6 +263,10 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SME_TMOP,
/* SME MOP4 instructions. */
AARCH64_FEATURE_SME_MOP4,
+ /* SVE2.3. */
+ AARCH64_FEATURE_SVE2p3,
+ /* SME2.3. */
+ AARCH64_FEATURE_SME2p3,
/* Virtual features. These are used to gate instructions that are enabled
by either of two (or more) sets of command line flags. */
@@ -290,6 +294,8 @@ enum aarch64_feature_bit {
AARCH64_FEATURE_SVE2p1_SME2p1,
/* +sve2p2 or +sme2p2 */
AARCH64_FEATURE_SVE2p2_SME2p2,
+ /* +sve2p3 or +sme2p3 */
+ AARCH64_FEATURE_SVE2p3_SME2p3,
AARCH64_NUM_FEATURES
};
@@ -879,11 +885,13 @@ enum aarch64_opnd
AARCH64_OPND_SME_Zm_17_3, /* SVE vector register in [19:17]*2+16. */
AARCH64_OPND_SME_Znx2_6_3, /* SVE vector register list from [8:6]*2. */
AARCH64_OPND_SME_Zmx2_17_3, /* SVE vector register list from [19:17]*2+16. */
+ AARCH64_OPND_SME_ZmxN_INDEX_22, /* SVE vector register list in [20:16].with index in 22 */
AARCH64_OPND_SME_Zmx2, /* SVE vector register list from [20:17]*2. */
AARCH64_OPND_SME_Zmx4, /* SVE vector register list from [20:18]*4. */
AARCH64_OPND_SME_Znx2, /* SVE vector register list from [9:6]*2. */
AARCH64_OPND_SME_Znx2_BIT_INDEX, /* SVE vector register list encoding a bit index from [9:6]*2. */
AARCH64_OPND_SME_Znx4, /* SVE vector register list from [9:7]*4. */
+ AARCH64_OPND_SME_Zn7x3_UNTYPED, /* SVE vector register list from [9:7]. */
AARCH64_OPND_SME_Ztx2_STRIDED, /* SVE vector register list in [4:0]&23. */
AARCH64_OPND_SME_Ztx4_STRIDED, /* SVE vector register list in [4:0]&19. */
AARCH64_OPND_SME_ZAda_1b, /* SME <ZAda>.H, 1-bits. */
@@ -913,6 +921,7 @@ enum aarch64_opnd
AARCH64_OPND_SME_ADDR_RI_U4xVL, /* SME [<Xn|SP>{, #<imm>, MUL VL}]. */
AARCH64_OPND_SME_SM_ZA, /* SME {SM | ZA}. */
AARCH64_OPND_SME_PnT_Wm_imm, /* SME <Pn>.<T>[<Wm>, #<imm>]. */
+ AARCH64_OPND_SME_SHRIMM3, /* 3-bit right shift, bits [18:16]. */
AARCH64_OPND_SME_SHRIMM4, /* 4-bit right shift, bits [19:16]. */
AARCH64_OPND_SME_SHRIMM5, /* size + 5-bit right shift, bits [23:22,20:16]. */
AARCH64_OPND_SME_Zk_INDEX, /* Zk[index], bits [12:10,5:4]. */
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index b0611654ead..702ab81f4fb 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -1140,6 +1140,7 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sve_index (self, info, code, inst, errors);
case AARCH64_OPND_SVE_ZnxN:
case AARCH64_OPND_SVE_ZtxN:
+ case AARCH64_OPND_SME_Zn7x3_UNTYPED:
case AARCH64_OPND_SME_PdxN:
return aarch64_ins_sve_reglist (self, info, code, inst, errors);
case AARCH64_OPND_SME_Zdnx2:
@@ -1153,6 +1154,8 @@ aarch64_insert_operand (const aarch64_operand *self,
case AARCH64_OPND_SME_Znx4:
case AARCH64_OPND_SME_Pdx2:
return aarch64_ins_sve_aligned_reglist (self, info, code, inst, errors);
+ case AARCH64_OPND_SME_ZmxN_INDEX_22:
+ return aarch64_ins_sve_reglist_index (self, info, code, inst, errors);
case AARCH64_OPND_SME_Ztx2_STRIDED:
case AARCH64_OPND_SME_Ztx4_STRIDED:
return aarch64_ins_sve_strided_reglist (self, info, code, inst, errors);
@@ -1177,6 +1180,7 @@ aarch64_insert_operand (const aarch64_operand *self,
return aarch64_ins_sme_sm_za (self, info, code, inst, errors);
case AARCH64_OPND_SME_PnT_Wm_imm:
return aarch64_ins_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case AARCH64_OPND_SME_SHRIMM3:
case AARCH64_OPND_SME_SHRIMM4:
return aarch64_ins_plain_shrimm (self, info, code, inst, errors);
case AARCH64_OPND_MOPS_ADDR_Rd:
diff --git a/opcodes/aarch64-asm.c b/opcodes/aarch64-asm.c
index 0c8f4b36902..a6b3b55faf2 100644
--- a/opcodes/aarch64-asm.c
+++ b/opcodes/aarch64-asm.c
@@ -1351,6 +1351,21 @@ aarch64_ins_sve_strided_reglist (const aarch64_operand *self,
return true;
}
+/* Encode {Zn - Zm}[index]. The fields array specifies which field
+ to use for Zn. */
+bool
+aarch64_ins_sve_reglist_index (const aarch64_operand *self ATTRIBUTE_UNUSED,
+ const aarch64_opnd_info *info ATTRIBUTE_UNUSED, aarch64_insn *code ATTRIBUTE_UNUSED,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ assert (info->reglist.has_index);
+ insert_field (self->fields[0], code, info->reglist.first_regno, 0);
+ insert_field (FLD_imm1_22, code, info->reglane.index, 0);
+
+ return true;
+}
+
/* Encode <pattern>{, MUL #<amount>}. The fields array specifies which
fields to use for <pattern>. <amount> - 1 is encoded in the SVE_imm4
field. */
diff --git a/opcodes/aarch64-asm.h b/opcodes/aarch64-asm.h
index 104c5e8d7a2..4063fccfd74 100644
--- a/opcodes/aarch64-asm.h
+++ b/opcodes/aarch64-asm.h
@@ -98,6 +98,7 @@ AARCH64_DECL_OPD_INSERTER (ins_sve_index);
AARCH64_DECL_OPD_INSERTER (ins_sve_limm_mov);
AARCH64_DECL_OPD_INSERTER (ins_sve_quad_index);
AARCH64_DECL_OPD_INSERTER (ins_sve_reglist);
+AARCH64_DECL_OPD_INSERTER (ins_sve_reglist_index);
AARCH64_DECL_OPD_INSERTER (ins_sve_strided_reglist);
AARCH64_DECL_OPD_INSERTER (ins_sve_scale);
AARCH64_DECL_OPD_INSERTER (ins_sve_shlimm);
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index ecaea2d2fdb..0439a249349 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -513,19 +513,29 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 22) & 0x1) == 0)
+ if (((word >> 14) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x00x100xxxxxxxxxxxxxxxxx. */
- return A64_OPID_c0080000_zero_SME_list_of_64bit_tiles;
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x00x100xx0xxxxxxxxxxxxxx. */
+ return A64_OPID_c0080000_zero_SME_list_of_64bit_tiles;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x10x100xx0xxxxxxxxxxxxxx. */
+ return A64_OPID_c0480001_zero_SME_ZT0_LIST;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x1000000x10x100xxxxxxxxxxxxxxxxx. */
- return A64_OPID_c0480001_zero_SME_ZT0_LIST;
+ x1000000xx0x100xx1xxxxxxxxxxxxxx. */
+ return A64_OPID_c0c84000_luti6_SVE_Zd_SME_ZT0_SVE_Zn;
}
}
}
@@ -598,10 +608,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 15) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000x000101x00xxxxxxxxxxxxxx. */
- return A64_OPID_c08b0000_luti4_SME_Zdnx4_SME_ZT0_SME_Znx2_BIT_INDEX;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x000101000xxxxxxxxxxxxxx. */
+ return A64_OPID_c08a0000_luti6_SME_Zdnx4_SME_ZT0_SME_Zn7x3_UNTYPED;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000x000101100xxxxxxxxxxxxxx. */
+ return A64_OPID_c08b0000_luti4_SME_Zdnx4_SME_ZT0_SME_Znx2_BIT_INDEX;
+ }
}
else
{
@@ -633,10 +653,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 15) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000000xx01101x00xxxxxxxxxxxxxx. */
- return A64_OPID_c09b0000_luti4_SME_Ztx4_STRIDED_SME_ZT0_SME_Znx2_BIT_INDEX;
+ if (((word >> 16) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx01101000xxxxxxxxxxxxxx. */
+ return A64_OPID_c09a0000_luti6_SME_Ztx4_STRIDED_SME_ZT0_SME_Zn7x3_UNTYPED;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000000xx01101100xxxxxxxxxxxxxx. */
+ return A64_OPID_c09b0000_luti4_SME_Ztx4_STRIDED_SME_ZT0_SME_Znx2_BIT_INDEX;
+ }
}
else
{
@@ -7432,10 +7462,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx1x1101xxxxxxxxxx. */
- return A64_OPID_c120b400_sqdmulh_SME_Zdnx2_SME_Zdnx2_SME_Zmx2;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx101101xxxxxxxxxx. */
+ return A64_OPID_c120b400_sqdmulh_SME_Zdnx2_SME_Zdnx2_SME_Zmx2;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx111101xxxxxxxxxx. */
+ return A64_OPID_c120f400_luti6_SME_Zdnx4_SVE_ZnxN_SME_ZmxN_INDEX_22;
+ }
}
}
else
@@ -7449,10 +7489,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x1000001xx1xxxxx1x1111xxxxxxxxxx. */
- return A64_OPID_c120bc00_sqdmulh_SME_Zdnx4_SME_Zdnx4_SME_Zmx4;
+ if (((word >> 14) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx101111xxxxxxxxxx. */
+ return A64_OPID_c120bc00_sqdmulh_SME_Zdnx4_SME_Zdnx4_SME_Zmx4;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x1000001xx1xxxxx111111xxxxxxxxxx. */
+ return A64_OPID_c120fc00_luti6_SME_Ztx4_STRIDED_SVE_ZnxN_SME_ZmxN_INDEX_22;
+ }
}
}
}
@@ -13479,10 +13529,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x0xx0xxxxx000000xxxxxxxxxx. */
- return A64_OPID_44800000_sdot_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x00x0xxxxx000000xxxxxxxxxx. */
+ return A64_OPID_44400000_sdot_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x01x0xxxxx000000xxxxxxxxxx. */
+ return A64_OPID_44800000_sdot_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ }
}
else
{
@@ -13496,10 +13556,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x0xx0xxxxx000001xxxxxxxxxx. */
- return A64_OPID_44800400_udot_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x00x0xxxxx000001xxxxxxxxxx. */
+ return A64_OPID_44400400_udot_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x01x0xxxxx000001xxxxxxxxxx. */
+ return A64_OPID_44800400_udot_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ }
}
else
{
@@ -13646,10 +13716,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x00x1xxxxx000x00xxxxxxxxxx. */
- return A64_OPID_44201000_sqrdmlah_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x00x1xxxxx000000xxxxxxxxxx. */
+ return A64_OPID_44200000_sdot_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x00x1xxxxx000100xxxxxxxxxx. */
+ return A64_OPID_44201000_sqrdmlah_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX;
+ }
}
else
{
@@ -13663,10 +13743,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x00x1xxxxx000x01xxxxxxxxxx. */
- return A64_OPID_44201400_sqrdmlsh_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x00x1xxxxx000001xxxxxxxxxx. */
+ return A64_OPID_44200400_udot_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x00x1xxxxx000101xxxxxxxxxx. */
+ return A64_OPID_44201400_sqrdmlsh_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX;
+ }
}
else
{
@@ -15148,26 +15238,46 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 11) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x0xx0xxxxx110x01xxxxxxxxxx. */
- return A64_OPID_4400c400_uclamp_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx0xxxxx110001xxxxxxxxxx. */
+ return A64_OPID_4400c400_uclamp_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx0xxxxx110101xxxxxxxxxx. */
+ return A64_OPID_4400d400_sabal_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ }
}
else
{
- if (((word >> 23) & 0x1) == 0)
+ if (((word >> 12) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x00x0xxxxx110x11xxxxxxxxxx. */
- return A64_OPID_4400cc00_udot_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ if (((word >> 23) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x00x0xxxxx110011xxxxxxxxxx. */
+ return A64_OPID_4400cc00_udot_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x01x0xxxxx110011xxxxxxxxxx. */
+ return A64_OPID_4480cc00_udot_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX;
+ }
}
else
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- 010001x01x0xxxxx110x11xxxxxxxxxx. */
- return A64_OPID_4480cc00_udot_SVE_Zd_SVE_Zn_SVE_Zm3_19_INDEX;
+ 010001x0xx0xxxxx110111xxxxxxxxxx. */
+ return A64_OPID_4400dc00_uabal_SVE_Zd_SVE_Zn_SVE_Zm_16;
}
}
}
@@ -16235,10 +16345,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
{
if (((word >> 19) & 0x1) == 0)
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x0xx0x0000101xxxxxxxxxxxxx. */
- return A64_OPID_4480a000_urecpe_SVE_Zd_SVE_Pg3_SVE_Zn;
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx000000101xxxxxxxxxxxxx. */
+ return A64_OPID_4480a000_urecpe_SVE_Zd_SVE_Pg3_SVE_Zn;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x0xx010000101xxxxxxxxxxxxx. */
+ return A64_OPID_4410a000_subp_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5;
+ }
}
else
{
@@ -16668,10 +16788,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x0xx1xxxxx011x10xxxxxxxxxx. */
- return A64_OPID_04206800_smulh_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x0xx1xxxxx011010xxxxxxxxxx. */
+ return A64_OPID_04206800_smulh_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x0xx1xxxxx011110xxxxxxxxxx. */
+ return A64_OPID_04207800_addqp_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ }
}
}
else
@@ -16695,10 +16825,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 000001x0xx1xxxxx011x11xxxxxxxxxx. */
- return A64_OPID_04206c00_umulh_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x0xx1xxxxx011011xxxxxxxxxx. */
+ return A64_OPID_04206c00_umulh_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 000001x0xx1xxxxx011111xxxxxxxxxx. */
+ return A64_OPID_04207c00_addsubp_SVE_Zd_SVE_Zn_SVE_Zm_16;
+ }
}
}
}
@@ -21414,10 +21554,40 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10001x11x1xxxxx000xxxxxxxxxxxxx. */
- return A64_OPID_45b00800_sqrshrun_SVE_Zd_SME_Znx2_SME_SHRIMM4;
+ if (((word >> 11) & 0x1) == 0)
+ {
+ if (((word >> 12) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10001x11x1xxxxx00000xxxxxxxxxxx. */
+ return A64_OPID_45a00000_sqshrn_SVE_Zd_SME_Znx2_SVE_SHRIMM_UNPRED_22;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10001x11x1xxxxx00010xxxxxxxxxxx. */
+ return A64_OPID_45a01000_uqshrn_SVE_Zd_SME_Znx2_SVE_SHRIMM_UNPRED_22;
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10001x11x10xxxx000x1xxxxxxxxxxx. */
+ return A64_OPID_45a80800_sqrshrun_SVE_Zd_SME_Znx2_SME_SHRIMM3;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10001x11x11xxxx000x1xxxxxxxxxxx. */
+ return A64_OPID_45b00800_sqrshrun_SVE_Zd_SME_Znx2_SME_SHRIMM4;
+ }
+ }
}
}
}
@@ -22101,19 +22271,49 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- if (((word >> 12) & 0x1) == 0)
+ if (((word >> 11) & 0x1) == 0)
{
/* 33222222222211111111110000000000
10987654321098765432109876543210
- x10001x11x1xxxxx0010xxxxxxxxxxxx. */
- return A64_OPID_45b02800_sqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM4;
+ x10001x11x1xxxxx001x0xxxxxxxxxxx. */
+ return A64_OPID_45a02000_sqshrun_SVE_Zd_SME_Znx2_SVE_SHRIMM_UNPRED_22;
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- x10001x11x1xxxxx0011xxxxxxxxxxxx. */
- return A64_OPID_45b03800_uqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM4;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10001x11x10xxxx00101xxxxxxxxxxx. */
+ return A64_OPID_45a82800_sqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM3;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10001x11x11xxxx00101xxxxxxxxxxx. */
+ return A64_OPID_45b02800_sqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM4;
+ }
+ }
+ else
+ {
+ if (((word >> 20) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10001x11x10xxxx00111xxxxxxxxxxx. */
+ return A64_OPID_45a83800_uqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM3;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ x10001x11x11xxxx00111xxxxxxxxxxx. */
+ return A64_OPID_45b03800_uqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM4;
+ }
+ }
}
}
}
@@ -22249,10 +22449,30 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 010001x1xx1xxxxx101x11xxxxxxxxxx. */
- return A64_OPID_4520bc00_luti4_SVE_Zd_SVE_ZnxN_SVE_Zm2_22_INDEX;
+ if (((word >> 12) & 0x1) == 0)
+ {
+ if (((word >> 22) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1x01xxxxx101011xxxxxxxxxx. */
+ return A64_OPID_4520ac00_luti6_SVE_Zd_SVE_ZnxN_SVE_Zm_16;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1x11xxxxx101011xxxxxxxxxx. */
+ return A64_OPID_4560ac00_luti6_SVE_Zd_SVE_ZnxN_SVE_Zm1_23_INDEX;
+ }
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 010001x1xx1xxxxx101111xxxxxxxxxx. */
+ return A64_OPID_4520bc00_luti4_SVE_Zd_SVE_ZnxN_SVE_Zm2_22_INDEX;
+ }
}
}
}
@@ -23277,10 +23497,50 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x1xx0xx100001xxxxxxxxxxxxx. */
- return A64_OPID_65042000_fmaxnmv_SVE_Vd_SVE_Pg3_SVE_Zn;
+ if (((word >> 19) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x0100001xxxxxxxxxxxxx. */
+ return A64_OPID_65042000_fmaxnmv_SVE_Vd_SVE_Pg3_SVE_Zn;
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1100001x00xxxxxxxxxx. */
+ return A64_OPID_650c3000_scvtf_SVE_Zd_SVE_Zn;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1100001x10xxxxxxxxxx. */
+ return A64_OPID_650c3800_scvtflt_SVE_Zd_SVE_Zn;
+ }
+ }
+ else
+ {
+ if (((word >> 11) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1100001x01xxxxxxxxxx. */
+ return A64_OPID_650c3400_ucvtf_SVE_Zd_SVE_Zn;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1100001x11xxxxxxxxxx. */
+ return A64_OPID_650c3c00_ucvtflt_SVE_Zd_SVE_Zn;
+ }
+ }
+ }
}
}
else
@@ -23414,10 +23674,30 @@ aarch64_opcode_lookup_1 (uint32_t word)
}
else
{
- /* 33222222222211111111110000000000
- 10987654321098765432109876543210
- 011001x1xx0xx101001xxxxxxxxxxxxx. */
- return A64_OPID_65052000_fminnmv_SVE_Vd_SVE_Pg3_SVE_Zn;
+ if (((word >> 19) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x0101001xxxxxxxxxxxxx. */
+ return A64_OPID_65052000_fminnmv_SVE_Vd_SVE_Pg3_SVE_Zn;
+ }
+ else
+ {
+ if (((word >> 10) & 0x1) == 0)
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1101001xx0xxxxxxxxxx. */
+ return A64_OPID_650d3000_fcvtzsn_SVE_Zd_SME_Znx2;
+ }
+ else
+ {
+ /* 33222222222211111111110000000000
+ 10987654321098765432109876543210
+ 011001x1xx0x1101001xx1xxxxxxxxxx. */
+ return A64_OPID_650d3400_fcvtzun_SVE_Zd_SME_Znx2;
+ }
+ }
}
}
else
@@ -37570,6 +37850,7 @@ aarch64_extract_operand (const aarch64_operand *self,
return aarch64_ext_sve_index (self, info, code, inst, errors);
case AARCH64_OPND_SVE_ZnxN:
case AARCH64_OPND_SVE_ZtxN:
+ case AARCH64_OPND_SME_Zn7x3_UNTYPED:
case AARCH64_OPND_SME_PdxN:
return aarch64_ext_sve_reglist (self, info, code, inst, errors);
case AARCH64_OPND_SME_Zdnx2:
@@ -37583,6 +37864,8 @@ aarch64_extract_operand (const aarch64_operand *self,
case AARCH64_OPND_SME_Znx4:
case AARCH64_OPND_SME_Pdx2:
return aarch64_ext_sve_aligned_reglist (self, info, code, inst, errors);
+ case AARCH64_OPND_SME_ZmxN_INDEX_22:
+ return aarch64_ext_sve_reglist_index (self, info, code, inst, errors);
case AARCH64_OPND_SME_Ztx2_STRIDED:
case AARCH64_OPND_SME_Ztx4_STRIDED:
return aarch64_ext_sve_strided_reglist (self, info, code, inst, errors);
@@ -37607,6 +37890,7 @@ aarch64_extract_operand (const aarch64_operand *self,
return aarch64_ext_sme_sm_za (self, info, code, inst, errors);
case AARCH64_OPND_SME_PnT_Wm_imm:
return aarch64_ext_sme_pred_reg_with_index (self, info, code, inst, errors);
+ case AARCH64_OPND_SME_SHRIMM3:
case AARCH64_OPND_SME_SHRIMM4:
return aarch64_ext_plain_shrimm (self, info, code, inst, errors);
case AARCH64_OPND_MOPS_ADDR_Rd:
diff --git a/opcodes/aarch64-dis.c b/opcodes/aarch64-dis.c
index c9e60a97152..b054e46b6f5 100644
--- a/opcodes/aarch64-dis.c
+++ b/opcodes/aarch64-dis.c
@@ -2353,6 +2353,23 @@ aarch64_ext_sve_reglist_zt (const aarch64_operand *self,
return true;
}
+/* Decode { <Zm1>-<Zm2> }[<index>]. The fields array specifies which field
+ to use for Zm. The opcode-dependent value specifies the number
+ of registers in the list. */
+bool
+aarch64_ext_sve_reglist_index (const aarch64_operand *self,
+ aarch64_opnd_info *info, aarch64_insn code,
+ const aarch64_inst *inst ATTRIBUTE_UNUSED,
+ aarch64_operand_error *errors ATTRIBUTE_UNUSED)
+{
+ info->reglist.first_regno = extract_field (self->fields[0], code, 0);
+ info->reglist.num_regs = get_opcode_dependent_value (inst->opcode);
+ info->reglist.stride = 1;
+ info->reglist.has_index = true;
+ info->reglist.index = extract_field (FLD_imm1_22, code, 0);
+ return true;
+}
+
/* Decode a strided register list. The first field holds the top bit
(0 or 16) and the second field holds the lower bits. The stride is
16 divided by the list length. */
@@ -3657,6 +3674,8 @@ aarch64_decode_variant_using_iclass (aarch64_inst *inst)
break;
case sve_shift_tsz_hsd:
+ /* This is also used for some instructions with hs variants only, in
+ which case FLD_SVE_sz will always be zero. */
i = extract_fields (inst->value, 0, 2, FLD_SVE_sz, FLD_SVE_tszl_19);
if (i == 0)
return false;
diff --git a/opcodes/aarch64-dis.h b/opcodes/aarch64-dis.h
index 9021113e2ab..7c53e0fbb06 100644
--- a/opcodes/aarch64-dis.h
+++ b/opcodes/aarch64-dis.h
@@ -122,6 +122,7 @@ AARCH64_DECL_OPD_EXTRACTOR (ext_sve_index);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_limm_mov);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_quad_index);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist);
+AARCH64_DECL_OPD_EXTRACTOR (ext_sve_reglist_index);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_strided_reglist);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_scale);
AARCH64_DECL_OPD_EXTRACTOR (ext_sve_shlimm);
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c
index 7f3b25eae38..1d963e1860c 100644
--- a/opcodes/aarch64-opc-2.c
+++ b/opcodes/aarch64-opc-2.c
@@ -288,11 +288,13 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zm_17_3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_1, FLD_SME_Zm17_3, FLD_CONST_0}, "an SVE vector register"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_6_3", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_0, FLD_SME_Zn6_3, FLD_CONST_0}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2_17_3", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CONST_1, FLD_SME_Zm17_3, FLD_CONST_0}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_ZmxN_INDEX_22", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_Zm_16, FLD_imm1_22}, "a list of SVE vector registers with index"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm2, FLD_CONST_0}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zmx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zm4, FLD_CONST_00}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2, FLD_CONST_0}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx2_BIT_INDEX", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn2, FLD_CONST_0}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Znx4", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4, FLD_CONST_00}, "a list of SVE vector registers"},
+ {AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Zn7x3_UNTYPED", 3 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Zn4, FLD_CONST_00}, "a list of untyped SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx2_STRIDED", 2 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt3}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REGLIST, "SME_Ztx4_STRIDED", 4 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZtT, FLD_SME_Zt2}, "a list of SVE vector registers"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_ZAda_1b", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_ZAda_1b}, "an SME ZA tile ZA0-ZA1"},
@@ -322,6 +324,7 @@ const struct aarch64_operand aarch64_operands[] =
{AARCH64_OPND_CLASS_ADDRESS, "SME_ADDR_RI_U4xVL", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn,FLD_imm4_0}, "memory offset"},
{AARCH64_OPND_CLASS_ADDRESS, "SME_SM_ZA", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CRm}, "streaming mode"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_PnT_Wm_imm", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl}, "Source scalable predicate register with index "},
+ {AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM3", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm3}, "a shift-right immediate operand"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM4", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_imm4}, "a shift-right immediate operand"},
{AARCH64_OPND_CLASS_IMMEDIATE, "SME_SHRIMM5", 1 << OPD_F_OD_LSB | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_SVE_tszh,FLD_SVE_imm5b}, "a shift-right immediate operand"},
{AARCH64_OPND_CLASS_SVE_REG, "SME_Zk_INDEX", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_imm2_4, FLD_CONST_1, FLD_SVE_i3l2, FLD_CONST_1, FLD_imm2_10}, "an indexed SVE vector register"},
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index b074765920e..0a81b0f21c1 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -361,6 +361,7 @@ const aarch64_field aarch64_fields[] =
AARCH64_FIELD (14, 1), /* imm1_14: general immediate in bits [14]. */
AARCH64_FIELD (15, 1), /* imm1_15: general immediate in bits [15]. */
AARCH64_FIELD (16, 1), /* imm1_16: general immediate in bits [16]. */
+ AARCH64_FIELD (22, 1), /* imm1_22: general immediate in bits [22]. */
AARCH64_FIELD ( 0, 2), /* imm2_0: general immediate in bits [1:0]. */
AARCH64_FIELD ( 1, 2), /* imm2_1: general immediate in bits [2:1]. */
AARCH64_FIELD ( 2, 2), /* imm2_2: general immediate in bits [3:2]. */
@@ -2072,6 +2073,13 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
return false;
break;
+ case AARCH64_OPND_SME_ZmxN_INDEX_22:
+ case AARCH64_OPND_SME_Zn7x3_UNTYPED:
+ num = get_operand_specific_data (&aarch64_operands[type]);
+ if (!check_reglist (opnd, mismatch_detail, idx, num, 1))
+ return false;
+ break;
+
default:
abort ();
}
@@ -3257,6 +3265,7 @@ operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
}
break;
+ case AARCH64_OPND_SME_SHRIMM3:
case AARCH64_OPND_SME_SHRIMM4:
size = 1 << get_operand_fields_width (get_operand_from_code (type));
if (!value_in_range_p (opnd->imm.value, 1, size))
@@ -4410,9 +4419,11 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_SME_Zmx2_17_3:
case AARCH64_OPND_SME_Zmx2:
case AARCH64_OPND_SME_Zmx4:
+ case AARCH64_OPND_SME_ZmxN_INDEX_22:
case AARCH64_OPND_SME_Znx2:
case AARCH64_OPND_SME_Znx2_BIT_INDEX:
case AARCH64_OPND_SME_Znx4:
+ case AARCH64_OPND_SME_Zn7x3_UNTYPED:
case AARCH64_OPND_SME_Ztx2_STRIDED:
case AARCH64_OPND_SME_Ztx4_STRIDED:
print_register_list (buf, size, opnd, "z", styler);
@@ -4617,6 +4628,7 @@ aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
case AARCH64_OPND_FBITS:
case AARCH64_OPND_TME_UIMM16:
case AARCH64_OPND_SIMM5:
+ case AARCH64_OPND_SME_SHRIMM3:
case AARCH64_OPND_SME_SHRIMM4:
case AARCH64_OPND_SME_SHRIMM5:
case AARCH64_OPND_SVE_SHLIMM_PRED:
diff --git a/opcodes/aarch64-opc.h b/opcodes/aarch64-opc.h
index 5d544d53baf..6d67190ff60 100644
--- a/opcodes/aarch64-opc.h
+++ b/opcodes/aarch64-opc.h
@@ -165,6 +165,7 @@ enum aarch64_field_kind
FLD_imm1_14,
FLD_imm1_15,
FLD_imm1_16,
+ FLD_imm1_22,
FLD_imm2_0,
FLD_imm2_1,
FLD_imm2_2,
diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h
index 1263f1f9bd8..150dec8c4f7 100644
--- a/opcodes/aarch64-tbl-2.h
+++ b/opcodes/aarch64-tbl-2.h
@@ -3995,5 +3995,33 @@ enum aarch64_opcode_idx
A64_OPID_a1c00018_usmop4s_SME_ZAda_3b_SME_Zn_6_3_SME_Zm_17_3,
A64_OPID_a1c00218_usmop4s_SME_ZAda_3b_SME_Znx2_6_3_SME_Zm_17_3,
A64_OPID_a1d00218_usmop4s_SME_ZAda_3b_SME_Znx2_6_3_SME_Zmx2_17_3,
+ A64_OPID_4520ac00_luti6_SVE_Zd_SVE_ZnxN_SVE_Zm_16,
+ A64_OPID_c120f400_luti6_SME_Zdnx4_SVE_ZnxN_SME_ZmxN_INDEX_22,
+ A64_OPID_c120fc00_luti6_SME_Ztx4_STRIDED_SVE_ZnxN_SME_ZmxN_INDEX_22,
+ A64_OPID_c08a0000_luti6_SME_Zdnx4_SME_ZT0_SME_Zn7x3_UNTYPED,
+ A64_OPID_c09a0000_luti6_SME_Ztx4_STRIDED_SME_ZT0_SME_Zn7x3_UNTYPED,
+ A64_OPID_c0c84000_luti6_SVE_Zd_SME_ZT0_SVE_Zn,
+ A64_OPID_04207800_addqp_SVE_Zd_SVE_Zn_SVE_Zm_16,
+ A64_OPID_04207c00_addsubp_SVE_Zd_SVE_Zn_SVE_Zm_16,
+ A64_OPID_4400d400_sabal_SVE_Zd_SVE_Zn_SVE_Zm_16,
+ A64_OPID_650c3000_scvtf_SVE_Zd_SVE_Zn,
+ A64_OPID_650c3800_scvtflt_SVE_Zd_SVE_Zn,
+ A64_OPID_44400000_sdot_SVE_Zd_SVE_Zn_SVE_Zm_16,
+ A64_OPID_44200000_sdot_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX,
+ A64_OPID_4410a000_subp_SVE_Zd_SVE_Pg3_SVE_Zd_SVE_Zm_5,
+ A64_OPID_4400dc00_uabal_SVE_Zd_SVE_Zn_SVE_Zm_16,
+ A64_OPID_650c3400_ucvtf_SVE_Zd_SVE_Zn,
+ A64_OPID_650c3c00_ucvtflt_SVE_Zd_SVE_Zn,
+ A64_OPID_44400400_udot_SVE_Zd_SVE_Zn_SVE_Zm_16,
+ A64_OPID_44200400_udot_SVE_Zd_SVE_Zn_SVE_Zm3_22_INDEX,
+ A64_OPID_650d3000_fcvtzsn_SVE_Zd_SME_Znx2,
+ A64_OPID_650d3400_fcvtzun_SVE_Zd_SME_Znx2,
+ A64_OPID_4560ac00_luti6_SVE_Zd_SVE_ZnxN_SVE_Zm1_23_INDEX,
+ A64_OPID_45a82800_sqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM3,
+ A64_OPID_45a80800_sqrshrun_SVE_Zd_SME_Znx2_SME_SHRIMM3,
+ A64_OPID_45a00000_sqshrn_SVE_Zd_SME_Znx2_SVE_SHRIMM_UNPRED_22,
+ A64_OPID_45a02000_sqshrun_SVE_Zd_SME_Znx2_SVE_SHRIMM_UNPRED_22,
+ A64_OPID_45a83800_uqrshrn_SVE_Zd_SME_Znx2_SME_SHRIMM3,
+ A64_OPID_45a01000_uqshrn_SVE_Zd_SME_Znx2_SVE_SHRIMM_UNPRED_22,
A64_OPID_MAX,
};
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 2fc69c27791..a7d49d8ceaa 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -1812,6 +1812,10 @@
{ \
QLF3(S_H,S_S,NIL), \
}
+#define OP_SVE_BHU \
+{ \
+ QLF3(S_B,S_H,NIL), \
+}
#define OP_SVE_HU \
{ \
QLF2(S_H,NIL), \
@@ -2119,6 +2123,11 @@
QLF3(S_B,S_S,NIL), \
QLF3(S_H,S_D,NIL), \
}
+#define OP_SVE_VVU_BH_HS \
+{ \
+ QLF3(S_B,S_H,NIL), \
+ QLF3(S_H,S_S,NIL), \
+}
#define OP_SVE_VVU_HSD_BHS \
{ \
QLF3(S_H,S_B,NIL), \
@@ -3057,6 +3066,12 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_f8f32 =
AARCH64_FEATURES (2, SME_MOP4, SME_F8F32);
static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
AARCH64_FEATURES (2, SME_MOP4, SME_I16I64);
+static const aarch64_feature_set aarch64_feature_sve2p3 =
+ AARCH64_FEATURE (SVE2p3);
+static const aarch64_feature_set aarch64_feature_sme2p3 =
+ AARCH64_FEATURE (SME2p3);
+static const aarch64_feature_set aarch64_feature_sve2p3_sme2p3 =
+ AARCH64_FEATURE (SVE2p3_SME2p3);
#define CORE &aarch64_feature_v8
#define FP &aarch64_feature_fp
@@ -3181,6 +3196,9 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
#define SME_MOP4_F8F16 &aarch64_feature_sme_mop4_f8f16
#define SME_MOP4_F8F32 &aarch64_feature_sme_mop4_f8f32
#define SME_MOP4_I16I64 &aarch64_feature_sme_mop4_i16i64
+#define SVE2p3 &aarch64_feature_sve2p3
+#define SME2p3 &aarch64_feature_sme2p3
+#define SVE2p3_SME2p3 &aarch64_feature_sve2p3_sme2p3
#define CORE_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS) \
{ NAME, OPCODE, MASK, CLASS, OP, CORE, OPS, QUALS, FLAGS | F_INVALID_IMM_SYMS_1, 0, 0, NULL }
@@ -3510,6 +3528,16 @@ static const aarch64_feature_set aarch64_feature_sme_mop4_i16i64 =
#define SME_MOP4_I16I64_INSN(NAME,OPCODE,MASK,CLASS,OPS,QUALS,FLAGS,TIED) \
{ NAME, OPCODE, MASK, CLASS, 0, SME_MOP4_I16I64, OPS, QUALS, \
FLAGS | F_STRICT, 0, TIED, NULL }
+#define SVE2p3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS, TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2p3, OPS, QUALS, \
+ F_STRICT | FLAGS, CONSTRAINTS, TIED, NULL }
+#define SME2p3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS, TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SME2p3, OPS, QUALS, \
+ FLAGS, CONSTRAINTS, TIED, NULL }
+#define SVE2p3_SME2p3_INSN(NAME,OPCODE,MASK,CLASS,OP,OPS,QUALS,FLAGS,CONSTRAINTS, TIED) \
+ { NAME, OPCODE, MASK, CLASS, OP, SVE2p3_SME2p3, OPS, QUALS, \
+ F_STRICT | F_INVALID_IMM_SYMS_3 | FLAGS, CONSTRAINTS, TIED, NULL }
+
#define MOPS_CPY_OP1_OP2_PME_INSN(NAME, OPCODE, MASK, FLAGS, CONSTRAINTS) \
MOPS_INSN (NAME, OPCODE, MASK, 0, \
@@ -7738,6 +7766,40 @@ const struct aarch64_opcode aarch64_opcode_table[] =
SME_MOP4_I16I64_INSN ("usmop4s", 0xa1c00218, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Znx2_6_3, SME_Zm_17_3), OP_SVE_DHH, 0, 0),
SME_MOP4_I16I64_INSN ("usmop4s", 0xa1d00218, 0xfff1fe38, sme_misc, OP3 (SME_ZAda_3b, SME_Znx2_6_3, SME_Zmx2_17_3), OP_SVE_DHH, 0, 0),
+ /* SVE2p3 instructions. */
+ SVE2p3_INSN ("luti6", 0x4520ac00, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm_16), OP_SVE_BBU, F_OD(2), 0, 0),
+
+ /* SME2p3 instructions. */
+ SME2p3_INSN ("luti6", 0xc120f400, 0xffa0fc03, sve_misc, 0, OP3 (SME_Zdnx4, SVE_ZnxN, SME_ZmxN_INDEX_22), OP_SVE_HHU, F_OD(2), 0, 0),
+ SME2p3_INSN ("luti6", 0xc120fc00, 0xffa0fc0c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SVE_ZnxN, SME_ZmxN_INDEX_22), OP_SVE_HHU, F_OD(2), 0, 0),
+ SME2p3_INSN ("luti6", 0xc08a0000, 0xfffffc63, sve_misc, 0, OP3 (SME_Zdnx4, SME_ZT0, SME_Zn7x3_UNTYPED), OP_SVE_BBU, F_OD(3), 0, 0),
+ SME2p3_INSN ("luti6", 0xc09a0000, 0xfffffc6c, sve_misc, 0, OP3 (SME_Ztx4_STRIDED, SME_ZT0, SME_Zn7x3_UNTYPED), OP_SVE_BBU, F_OD(3), 0, 0),
+ SME2p3_INSN ("luti6", 0xc0c84000, 0xfffffc00, sve_misc, 0, OP3 (SVE_Zd, SME_ZT0, SVE_Zn), OP_SVE_BUU, 0, 0, 0),
+
+ /* SME2p3 / SME2p3 instructions. */
+ SVE2p3_SME2p3_INSN ("addqp", 0x04207800, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0, 0),
+ SVE2p3_SME2p3_INSN ("addsubp", 0x04207c00, 0xff20fc00, sve_size_bhsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_BHSD, 0, 0, 0),
+ SVE2p3_SME2p3_INSN ("sabal", 0x4400d400, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p3_SME2p3_INSN ("scvtf", 0x650c3000, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0, 0),
+ SVE2p3_SME2p3_INSN ("scvtflt", 0x650c3800, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0, 0),
+ SVE2p3_SME2p3_INSN ("sdot", 0x44400000, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p3_SME2p3_INSN ("sdot", 0x44200000, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p3_SME2p3_INSN ("subp", 0x4410a000, 0xff3fe000, sve_size_bhsd, 0, OP4 (SVE_Zd, SVE_Pg3, SVE_Zd, SVE_Zm_5), OP_SVE_VMVV_BHSD, 0, C_SCAN_MOVPRFX, 2),
+ SVE2p3_SME2p3_INSN ("uabal", 0x4400dc00, 0xff20fc00, sve_size_hsd, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_HSD_BHS, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p3_SME2p3_INSN ("ucvtf", 0x650c3400, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0, 0),
+ SVE2p3_SME2p3_INSN ("ucvtflt", 0x650c3c00, 0xff3ffc00, sve_size_hsd, 0, OP2 (SVE_Zd, SVE_Zn), OP_SVE_VV_HSD_BHS, 0, 0, 0),
+ SVE2p3_SME2p3_INSN ("udot", 0x44400400, 0xffe0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p3_SME2p3_INSN ("udot", 0x44200400, 0xffa0fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_22_INDEX), OP_SVE_VVV_H_B, 0, C_SCAN_MOVPRFX, 0),
+ SVE2p3_SME2p3_INSN ("fcvtzsn", 0x650d3000, 0xff3ffc20, sve_size_hsd, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_VV_BHS_HSD, 0, 0, 0),
+ SVE2p3_SME2p3_INSN ("fcvtzun", 0x650d3400, 0xff3ffc20, sve_size_hsd, 0, OP2 (SVE_Zd, SME_Znx2), OP_SVE_VV_BHS_HSD, 0, 0, 0),
+ SVE2p3_SME2p3_INSN ("luti6", 0x4560ac00, 0xff60fc00, sve_misc, 0, OP3 (SVE_Zd, SVE_ZnxN, SVE_Zm1_23_INDEX), OP_SVE_HHU, F_OD(2), 0, 0),
+ SVE2p3_SME2p3_INSN ("sqrshrn", 0x45a82800, 0xfff8fc20, sve_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM3), OP_SVE_BHU, 0, 0, 0),
+ SVE2p3_SME2p3_INSN ("sqrshrun", 0x45a80800, 0xfff8fc20, sve_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM3), OP_SVE_BHU, 0, 0, 0),
+ SVE2p3_SME2p3_INSN ("sqshrn", 0x45a00000, 0xffe0fc20, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SME_Znx2, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BH_HS, 0, 0, 0),
+ SVE2p3_SME2p3_INSN ("sqshrun", 0x45a02000, 0xffe0fc20, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SME_Znx2, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BH_HS, 0, 0, 0),
+ SVE2p3_SME2p3_INSN ("uqrshrn", 0x45a83800, 0xfff8fc20, sve_misc, 0, OP3 (SVE_Zd, SME_Znx2, SME_SHRIMM3), OP_SVE_BHU, 0, 0, 0),
+ SVE2p3_SME2p3_INSN ("uqshrn", 0x45a01000, 0xffe0fc20, sve_shift_tsz_hsd, 0, OP3 (SVE_Zd, SME_Znx2, SVE_SHRIMM_UNPRED_22), OP_SVE_VVU_BH_HS, 0, 0, 0),
+
{0, 0, 0, 0, 0, 0, {}, {}, 0, 0, 0, NULL},
};
@@ -8305,6 +8367,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2_17_3", \
2 << OPD_F_OD_LSB, F(FLD_CONST_1, FLD_SME_Zm17_3, FLD_CONST_0), \
"a list of SVE vector registers") \
+ Y(SVE_REGLIST, sve_reglist_index, "SME_ZmxN_INDEX_22", 2 << OPD_F_OD_LSB, \
+ F(FLD_SVE_Zm_16, FLD_imm1_22), "a list of SVE vector registers with index") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx2", 2 << OPD_F_OD_LSB, \
F(FLD_SME_Zm2, FLD_CONST_0), "a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Zmx4", 4 << OPD_F_OD_LSB, \
@@ -8316,6 +8380,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
"a list of SVE vector registers") \
Y(SVE_REGLIST, sve_aligned_reglist, "SME_Znx4", 4 << OPD_F_OD_LSB, \
F(FLD_SME_Zn4, FLD_CONST_00), "a list of SVE vector registers") \
+ Y(SVE_REGLIST, sve_reglist, "SME_Zn7x3_UNTYPED", 3 << OPD_F_OD_LSB, \
+ F(FLD_SME_Zn4, FLD_CONST_00), "a list of untyped SVE vector registers") \
Y(SVE_REGLIST, sve_strided_reglist, "SME_Ztx2_STRIDED", \
2 << OPD_F_OD_LSB, F(FLD_SME_ZtT, FLD_SME_Zt3), \
"a list of SVE vector registers") \
@@ -8384,6 +8450,8 @@ const struct aarch64_opcode aarch64_opcode_table[] =
Y(SVE_REG, sme_pred_reg_with_index, "SME_PnT_Wm_imm", 0, \
F(FLD_SME_Rm,FLD_SVE_Pn,FLD_SME_i1,FLD_SME_tszh,FLD_SME_tszl), \
"Source scalable predicate register with index ") \
+ Y(IMMEDIATE, plain_shrimm, "SME_SHRIMM3", 0, F(FLD_SVE_imm3), \
+ "a shift-right immediate operand") \
Y(IMMEDIATE, plain_shrimm, "SME_SHRIMM4", 0, F(FLD_SVE_imm4), \
"a shift-right immediate operand") \
Y(IMMEDIATE, sve_shrimm, "SME_SHRIMM5", 1 << OPD_F_OD_LSB, \
--
2.43.0
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