[PATCH 2/2] Regenerated files for FEAT_LSCP

[Alice Carlotti]

On Wed, Nov 19, 2025 at 05:42:44PM +0000, richard.ball@arm.com wrote:
> From: Richard Ball <Richard.Ball@arm.com>
> 
> ---
>  opcodes/aarch64-dis-2.c | 46 ++++++++++++++++++++++++++++++++++-------
>  opcodes/aarch64-tbl-2.h |  3 +++
>  2 files changed, 41 insertions(+), 8 deletions(-)

Since we switched to using enums instead of raw integers for opcode and operand
numbers, these generated diffs have become much smaller, so I don't think it's
worth posting them as a separate patch.

Alice

> 
> diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
> index ecaea2d2fdb..80f14b37af4 100644
> --- a/opcodes/aarch64-dis-2.c
> +++ b/opcodes/aarch64-dis-2.c
> @@ -10627,10 +10627,20 @@ aarch64_opcode_lookup_1 (uint32_t word)
>                                          {
>                                            if (((word >> 21) & 0x1) == 0)
>                                              {
> -                                              /* 33222222222211111111110000000000
> -                                                 10987654321098765432109876543210
> -                                                 xx011001000xxxxxxxxx10xxxxxxxxxx.  */
> -                                              return A64_OPID_19000800_stilp_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB;
> +                                              if (((word >> 14) & 0x1) == 0)
> +                                                {
> +                                                  /* 33222222222211111111110000000000
> +                                                     10987654321098765432109876543210
> +                                                     xx011001000xxxxxx0xx10xxxxxxxxxx.  */
> +                                                  return A64_OPID_19000800_stilp_Rt_Rs_RCPC3_ADDR_OPT_PREIND_WB;
> +                                                }
> +                                              else
> +                                                {
> +                                                  /* 33222222222211111111110000000000
> +                                                     10987654321098765432109876543210
> +                                                     xx011001000xxxxxx1xx10xxxxxxxxxx.  */
> +                                                  return A64_OPID_d9005800_stlp_Rt_Rs_ADDR_SIMPLE;
> +                                                }
>                                              }
>                                            else
>                                              {
> @@ -11084,10 +11094,30 @@ aarch64_opcode_lookup_1 (uint32_t word)
>                                          {
>                                            if (((word >> 21) & 0x1) == 0)
>                                              {
> -                                              /* 33222222222211111111110000000000
> -                                                 10987654321098765432109876543210
> -                                                 xx011001010xxxxxxxxx10xxxxxxxxxx.  */
> -                                              return A64_OPID_19400800_ldiapp_Rt_Rs_RCPC3_ADDR_OPT_POSTIND;
> +                                              if (((word >> 13) & 0x1) == 0)
> +                                                {
> +                                                  if (((word >> 14) & 0x1) == 0)
> +                                                    {
> +                                                      /* 33222222222211111111110000000000
> +                                                         10987654321098765432109876543210
> +                                                         xx011001010xxxxxx00x10xxxxxxxxxx.  */
> +                                                      return A64_OPID_19400800_ldiapp_Rt_Rs_RCPC3_ADDR_OPT_POSTIND;
> +                                                    }
> +                                                  else
> +                                                    {
> +                                                      /* 33222222222211111111110000000000
> +                                                         10987654321098765432109876543210
> +                                                         xx011001010xxxxxx10x10xxxxxxxxxx.  */
> +                                                      return A64_OPID_d9405800_ldap_Rt_Rs_ADDR_SIMPLE;
> +                                                    }
> +                                                }
> +                                              else
> +                                                {
> +                                                  /* 33222222222211111111110000000000
> +                                                     10987654321098765432109876543210
> +                                                     xx011001010xxxxxxx1x10xxxxxxxxxx.  */
> +                                                  return A64_OPID_d9407800_ldapp_Rt_Rs_ADDR_SIMPLE;
> +                                                }
>                                              }
>                                            else
>                                              {
> diff --git a/opcodes/aarch64-tbl-2.h b/opcodes/aarch64-tbl-2.h
> index 1263f1f9bd8..c254440f323 100644
> --- a/opcodes/aarch64-tbl-2.h
> +++ b/opcodes/aarch64-tbl-2.h
> @@ -1057,6 +1057,9 @@ enum aarch64_opcode_idx
>    A64_OPID_889f7c00_stllr_Rt_ADDR_SIMPLE,
>    A64_OPID_089f7c00_stllrb_Rt_ADDR_SIMPLE,
>    A64_OPID_489f7c00_stllrh_Rt_ADDR_SIMPLE,
> +  A64_OPID_d9405800_ldap_Rt_Rs_ADDR_SIMPLE,
> +  A64_OPID_d9407800_ldapp_Rt_Rs_ADDR_SIMPLE,
> +  A64_OPID_d9005800_stlp_Rt_Rs_ADDR_SIMPLE,
>    A64_OPID_28000000_stnp_Rt_Rt2_ADDR_SIMM7,
>    A64_OPID_28400000_ldnp_Rt_Rt2_ADDR_SIMM7,
>    A64_OPID_2c000000_stnp_Ft_Ft2_ADDR_SIMM7,
> -- 
> 2.34.1
>