[PATCH 1/4] x86: sub-divide APX_F - NCI

[Jiang, Haochen]

> From: Jiang, Haochen
> Sent: Monday, December 1, 2025 3:50 PM
> 
> > From: Jan Beulich <jbeulich@suse.com>
> > Sent: Monday, December 1, 2025 3:46 PM
> >
> > On 01.12.2025 07:31, Jiang, Haochen wrote:
> > >> From: Jan Beulich <jbeulich@suse.com>
> > >> Sent: Friday, November 28, 2025 5:00 PM
> > >
> > > I checked SDM for legacy CMOVcc. In the description part, we have:
> > >
> > > "The CMOVcc instructions were introduced in P6 family processors;
> > > however, these instructions may not be supported by all IA-32 processors.
> > > Software can determine if the CMOVcc instructions are supported by
> > checking
> > > the processor’s feature information with the CPUID instruction
> > > (see “CPUID—CPU Identification” in this chapter)."
> > >
> > > In CPUID section, we could see the CMOV bit. Thus, the legacy CMOVcc is
> > > controlled by a CPUID. As its direct APX_F extension, I suppose we still
> need
> > > to base on CMOV.
> >
> > Then you need to have the APX spec updated accordingly. My (recently
> > derived)
> > understanding is that omitting CMOV may have been deliberate: While
> related
> > to the legacy CMOVcc, they're apparently meant to be part of the NCI sub-
> > extension alone, with no other qualification needed.
> >
> 
> That is also another understanding. I have written an email to documentation
> team for clarification on that. Let's wait and see.
> 

Let's omit CMOV first for now. There are also two opinions on this in our
internal discussion and seems still need time to make decision. Since it is easy
to add CMOV back if we decide to add them in doc, I would not want to block
the patch due to this.

Thx,
Haochen

> 
> > As to the SDM - it's not clear to me at all why CMOVcc's table there doesn't
> > have a CPUID column, like other insns have.
> >
> > Jan