[PATCH v1] PowerPC: Support for Additional Performance Monitor Counters (RFC02666)
Surya Kumari Jangala
jskumari@linux.ibm.com
Mon Dec 1 11:20:41 GMT 2025
I am not able to apply the patch. You have to resend again.
-Surya
On 13/11/25 3:25 pm, Abhay Kandpal wrote:
> opcodes/
> * ppc-opc.c (powerpc_opcodes): Add mtummcrae, mtummcr2e, mtmmcr2e
> mtmmcrae, mtmmcr1e, mtmmcr3e, mtupmc7, mtupmc8, mtpmc7, mtpmc8,
> mfummcrae, mfmmcrae, mfummcr1e, mfmmcr1e, mfummcr2e, mfmmcr2e,
> mfummcr3e, mfmmcr3e, mfupmc7, mfpmc7, mfupmc8, mfpmc8.
>
> gas/
> * testsuite/gas/ppc/future.s: New test.
> * testsuite/gas/ppc/future.d: Likewise.
> ---
> This patch is reg tested.
>
> gas/testsuite/gas/ppc/future.d | 22 ++++++++++++++++++++++
> gas/testsuite/gas/ppc/future.s | 22 ++++++++++++++++++++++
> opcodes/ppc-opc.c | 22 ++++++++++++++++++++++
> 3 files changed, 66 insertions(+)
>
> diff --git a/gas/testsuite/gas/ppc/future.d b/gas/testsuite/gas/ppc/future.d
> index 19e96fac345..1ac66df69b8 100644
> --- a/gas/testsuite/gas/ppc/future.d
> +++ b/gas/testsuite/gas/ppc/future.d
> @@ -106,4 +106,26 @@ Disassembly of section \.text:
> .*: (83 b9 2f 12|12 2f b9 83) vupkint8tofp32 v17,v23,3
> .*: (da 9e 72 7c|7c 72 9e da) lxvpb32x vs34,r18,r19
> .*: (da af 74 7c|7c 74 af da) stxvpb32x vs34,r20,r21
> +.*: (a6 bb 23 7c|7c 23 bb a6) mtummcrae r1
> +.*: (a6 bb 45 7c|7c 45 bb a6) mtummcr2e r2
> +.*: (a6 bb 65 7c|7c 65 bb a6) mtummcr2e r3
> +.*: (a6 bb 93 7c|7c 93 bb a6) mtmmcrae r4
> +.*: (a6 bb b4 7c|7c b4 bb a6) mtmmcr1e r5
> +.*: (a6 bb d6 7c|7c d6 bb a6) mtmmcr3e r6
> +.*: (a6 c3 e9 7c|7c e9 c3 a6) mtupmc7 r7
> +.*: (a6 c3 0a 7d|7d 0a c3 a6) mtupmc8 r8
> +.*: (a6 c3 39 7d|7d 39 c3 a6) mtpmc7 r9
> +.*: (a6 c3 5a 7d|7d 5a c3 a6) mtpmc8 r10
> +.*: (a6 ba 63 7d|7d 63 ba a6) mfummcrae r11
> +.*: (a6 ba 83 7d|7d 83 ba a6) mfummcrae r12
> +.*: (a6 ba a4 7d|7d a4 ba a6) mfummcr1e r13
> +.*: (a6 ba c4 7d|7d c4 ba a6) mfummcr1e r14
> +.*: (a6 ba e5 7d|7d e5 ba a6) mfummcr2e r15
> +.*: (a6 ba 05 7e|7e 05 ba a6) mfummcr2e r16
> +.*: (a6 ba 26 7e|7e 26 ba a6) mfummcr3e r17
> +.*: (a6 ba 46 7e|7e 46 ba a6) mfummcr3e r18
> +.*: (a6 c2 69 7e|7e 69 c2 a6) mfupmc7 r19
> +.*: (a6 c2 89 7e|7e 89 c2 a6) mfupmc7 r20
> +.*: (a6 c2 aa 7e|7e aa c2 a6) mfupmc8 r21
> +.*: (a6 c2 ca 7e|7e ca c2 a6) mfupmc8 r22
> #pass
> diff --git a/gas/testsuite/gas/ppc/future.s b/gas/testsuite/gas/ppc/future.s
> index 492b963c96c..2ec933be673 100644
> --- a/gas/testsuite/gas/ppc/future.s
> +++ b/gas/testsuite/gas/ppc/future.s
> @@ -80,4 +80,26 @@ _start:
> vupkint8tofp32 17, 23, 3
> lxvpb32x 34, 18, 19
> stxvpb32x 34, 20, 21
> + mtummcrae 1
> + mtummcr2e 2
> + mtmmcr2e 3
> + mtmmcrae 4
> + mtmmcr1e 5
> + mtmmcr3e 6
> + mtupmc7 7
> + mtupmc8 8
> + mtpmc7 9
> + mtpmc8 10
> + mfummcrae 11
> + mfmmcrae 12
> + mfummcr1e 13
> + mfmmcr1e 14
> + mfummcr2e 15
> + mfmmcr2e 16
> + mfummcr3e 17
> + mfmmcr3e 18
> + mfupmc7 19
> + mfpmc7 20
> + mfupmc8 21
> + mfpmc8 22
>
> diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
> index 08d6a38d22f..c455b0cbbf4 100644
> --- a/opcodes/ppc-opc.c
> +++ b/opcodes/ppc-opc.c
> @@ -7922,6 +7922,14 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"mfsier3", XSPR(31,339,737), XSPR_MASK, POWER10, EXT, {RT}},
> {"mfummcr3", XSPR(31,339,738), XSPR_MASK, POWER10, EXT, {RT}},
> {"mfmmcr3", XSPR(31,339,738), XSPR_MASK, POWER10, EXT, {RT}},
> +{"mfummcrae", XSPR(31,339,739), XSPR_MASK, FUTURE, EXT, {RT}},
> +{"mfmmcrae", XSPR(31,339,739), XSPR_MASK, FUTURE, EXT, {RT}},
> +{"mfummcr1e", XSPR(31,339,740), XSPR_MASK, FUTURE, EXT, {RT}},
> +{"mfmmcr1e", XSPR(31,339,740), XSPR_MASK, FUTURE, EXT, {RT}},
> +{"mfummcr2e", XSPR(31,339,741), XSPR_MASK, FUTURE, EXT, {RT}},
> +{"mfmmcr2e", XSPR(31,339,741), XSPR_MASK, FUTURE, EXT, {RT}},
> +{"mfummcr3e", XSPR(31,339,742), XSPR_MASK, FUTURE, EXT, {RT}},
> +{"mfmmcr3e", XSPR(31,339,742), XSPR_MASK, FUTURE, EXT, {RT}},
> {"mfusier", XSPR(31,339,768), XSPR_MASK, POWER10, EXT, {RT}},
> {"mfsier", XSPR(31,339,768), XSPR_MASK, POWER10, EXT, {RT}},
> {"mfummcr2", XSPR(31,339,769), XSPR_MASK, POWER9, EXT, {RT}},
> @@ -7940,6 +7948,10 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"mfpmc5", XSPR(31,339,775), XSPR_MASK, POWER7, EXT, {RT}},
> {"mfupmc6", XSPR(31,339,776), XSPR_MASK, POWER9, EXT, {RT}},
> {"mfpmc6", XSPR(31,339,776), XSPR_MASK, POWER7, EXT, {RT}},
> +{"mfupmc7", XSPR(31,339,777), XSPR_MASK, FUTURE, EXT, {RT}},
> +{"mfpmc7", XSPR(31,339,777), XSPR_MASK, FUTURE, EXT, {RT}},
> +{"mfupmc8", XSPR(31,339,778), XSPR_MASK, FUTURE, EXT, {RT}},
> +{"mfpmc8", XSPR(31,339,778), XSPR_MASK, FUTURE, EXT, {RT}},
> {"mfummcr0", XSPR(31,339,779), XSPR_MASK, POWER9, EXT, {RS}},
> {"mfmmcr0", XSPR(31,339,779), XSPR_MASK, POWER7, EXT, {RS}},
> {"mfusiar", XSPR(31,339,780), XSPR_MASK, POWER9, EXT, {RS}},
> @@ -8383,9 +8395,15 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"mtmcsrr0", XSPR(31,467,570), XSPR_MASK, PPCRFMCI, EXT, {RS}},
> {"mtmcsrr1", XSPR(31,467,571), XSPR_MASK, PPCRFMCI, EXT, {RS}},
> {"mtmcsr", XSPR(31,467,572), XSPR_MASK, PPCRFMCI, EXT, {RS}},
> +{"mtummcrae", XSPR(31,467,739), XSPR_MASK, FUTURE, EXT, {RS}},
> +{"mtummcr2e", XSPR(31,467,741), XSPR_MASK, FUTURE, EXT, {RS}},
> +{"mtmmcr2e", XSPR(31,467,741), XSPR_MASK, FUTURE, EXT, {RS}},
> {"mtsier2", XSPR(31,467,752), XSPR_MASK, POWER10, EXT, {RS}},
> {"mtsier3", XSPR(31,467,753), XSPR_MASK, POWER10, EXT, {RS}},
> {"mtmmcr3", XSPR(31,467,754), XSPR_MASK, POWER10, EXT, {RS}},
> +{"mtmmcrae", XSPR(31,467,755), XSPR_MASK, FUTURE, EXT, {RS}},
> +{"mtmmcr1e", XSPR(31,467,756), XSPR_MASK, FUTURE, EXT, {RS}},
> +{"mtmmcr3e", XSPR(31,467,758), XSPR_MASK, FUTURE, EXT, {RS}},
> {"mtummcr2", XSPR(31,467,769), XSPR_MASK, POWER9, EXT, {RS}},
> {"mtmmcr2", XSPR(31,467,769), XSPR_MASK, POWER9, EXT, {RS}},
> {"mtummcra", XSPR(31,467,770), XSPR_MASK, POWER9, EXT, {RS}},
> @@ -8395,6 +8413,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"mtupmc4", XSPR(31,467,774), XSPR_MASK, POWER9, EXT, {RS}},
> {"mtupmc5", XSPR(31,467,775), XSPR_MASK, POWER9, EXT, {RS}},
> {"mtupmc6", XSPR(31,467,776), XSPR_MASK, POWER9, EXT, {RS}},
> +{"mtupmc7", XSPR(31,467,777), XSPR_MASK, FUTURE, EXT, {RS}},
> +{"mtupmc8", XSPR(31,467,778), XSPR_MASK, FUTURE, EXT, {RS}},
> {"mtummcr0", XSPR(31,467,779), XSPR_MASK, POWER9, EXT, {RS}},
> {"mtsier", XSPR(31,467,784), XSPR_MASK, POWER10, EXT, {RS}},
> {"mtmmcra", XSPR(31,467,786), XSPR_MASK, POWER7, EXT, {RS}},
> @@ -8404,6 +8424,8 @@ const struct powerpc_opcode powerpc_opcodes[] = {
> {"mtpmc4", XSPR(31,467,790), XSPR_MASK, POWER7, EXT, {RS}},
> {"mtpmc5", XSPR(31,467,791), XSPR_MASK, POWER7, EXT, {RS}},
> {"mtpmc6", XSPR(31,467,792), XSPR_MASK, POWER7, EXT, {RS}},
> +{"mtpmc7", XSPR(31,467,793), XSPR_MASK, FUTURE, EXT, {RS}},
> +{"mtpmc8", XSPR(31,467,794), XSPR_MASK, FUTURE, EXT, {RS}},
> {"mtmmcr0", XSPR(31,467,795), XSPR_MASK, POWER7, EXT, {RS}},
> {"mtsiar", XSPR(31,467,796), XSPR_MASK, POWER10, EXT, {RS}},
> {"mtsdar", XSPR(31,467,797), XSPR_MASK, POWER10, EXT, {RS}},
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