[RFC] RISC-V: Support Zvabd extension instructions.
Jiawei
jiawei@iscas.ac.cn
Mon Aug 18 11:29:25 GMT 2025
This patch supports Zvabd extension instructions:
https://github.com/riscv/integer-vector-absolute-difference
bfd/ChangeLog:
* elfxx-riscv.c (riscv_multi_subset_supports): New extension.
(riscv_multi_subset_supports_ext): Ditto.
gas/ChangeLog:
* NEWS: New extension.
* testsuite/gas/riscv/march-help.l: Ditto.
* testsuite/gas/riscv/zvabd.d: New test.
* testsuite/gas/riscv/zvabd.s: New test.
include/ChangeLog:
* opcode/riscv-opc.h (MATCH_VABS_V): New macro.
(MASK_VABS_V): Ditto.
(MATCH_VABD_VV): Ditto.
(MASK_VABD_VV): Ditto.
(MATCH_VABDU_VV): Ditto.
(MASK_VABDU_VV): Ditto.
(MATCH_VWABDACC_VV): Ditto.
(MASK_VWABDACC_VV): Ditto.
(MATCH_VWABDACCU_VV): Ditto.
(MASK_VWABDACCU_VV): Ditto.
* opcode/riscv.h (enum riscv_insn_class): New extension.
opcodes/ChangeLog:
* riscv-opc.c: New instructions.
---
bfd/elfxx-riscv.c | 5 +++++
gas/NEWS | 3 +++
gas/testsuite/gas/riscv/march-help.l | 1 +
gas/testsuite/gas/riscv/zvabd.d | 13 +++++++++++++
gas/testsuite/gas/riscv/zvabd.s | 6 ++++++
include/opcode/riscv-opc.h | 11 +++++++++++
include/opcode/riscv.h | 1 +
opcodes/riscv-opc.c | 7 +++++++
8 files changed, 47 insertions(+)
create mode 100644 gas/testsuite/gas/riscv/zvabd.d
create mode 100644 gas/testsuite/gas/riscv/zvabd.s
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c
index 35675735dca..9ee897991c6 100644
--- a/bfd/elfxx-riscv.c
+++ b/bfd/elfxx-riscv.c
@@ -1537,6 +1537,7 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] =
{"zvl16384b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl32768b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
+ {"zvabd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"ztso", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zca", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
{"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },
@@ -2960,6 +2961,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps,
return riscv_subset_supports (rps, "zvksed");
case INSN_CLASS_ZVKSH:
return riscv_subset_supports (rps, "zvksh");
+ case INSN_CLASS_ZVABD:
+ return riscv_subset_supports (rps, "zvabd");
case INSN_CLASS_ZCB:
return riscv_subset_supports (rps, "zcb");
case INSN_CLASS_ZCB_AND_ZBB:
@@ -3266,6 +3269,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps,
return _("zvksed");
case INSN_CLASS_ZVKSH:
return _("zvksh");
+ case INSN_CLASS_ZVABD:
+ return _("zvabd");
case INSN_CLASS_ZCB:
return "zcb";
case INSN_CLASS_ZCB_AND_ZBA:
diff --git a/gas/NEWS b/gas/NEWS
index a9858939f06..133bbb08321 100644
--- a/gas/NEWS
+++ b/gas/NEWS
@@ -2,6 +2,9 @@
* NaCl target support is removed.
+* Add support for RISC-V standard extensions:
+ Zvabd v1.0
+
Changes in 2.45:
* Add support to generate SFrame stack trace information (.sframe)
diff --git a/gas/testsuite/gas/riscv/march-help.l b/gas/testsuite/gas/riscv/march-help.l
index 709ccff2b7f..42182d92188 100644
--- a/gas/testsuite/gas/riscv/march-help.l
+++ b/gas/testsuite/gas/riscv/march-help.l
@@ -100,6 +100,7 @@ All available -march extensions for RISC-V:
zvl16384b 1.0
zvl32768b 1.0
zvl65536b 1.0
+ zvabd 1.0
ztso 1.0
zca 1.0
zcb 1.0
diff --git a/gas/testsuite/gas/riscv/zvabd.d b/gas/testsuite/gas/riscv/zvabd.d
new file mode 100644
index 00000000000..7cef2798c8c
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvabd.d
@@ -0,0 +1,13 @@
+#as: -march=rv64gc_zvabd
+#objdump: -dr
+
+.*:[ ]+file format .*
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ ]+[0-9a-f]+:[ ]+4a282257[ ]+vabs.v[ ]+v4,v2
+[ ]+[0-9a-f]+:[ ]+4620a257[ ]+vabd.vv[ ]+v4,v2,v1
+[ ]+[0-9a-f]+:[ ]+4e20a257[ ]+vabdu.vv[ ]+v4,v2,v1
+[ ]+[0-9a-f]+:[ ]+5620a257[ ]+vwabdacc.vv[ ]+v4,v2,v1
+[ ]+[0-9a-f]+:[ ]+5a20a257[ ]+vwabdaccu.vv[ ]+v4,v2,v1
diff --git a/gas/testsuite/gas/riscv/zvabd.s b/gas/testsuite/gas/riscv/zvabd.s
new file mode 100644
index 00000000000..a142c98b7f9
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zvabd.s
@@ -0,0 +1,6 @@
+target:
+ vabs.v v4, v2
+ vabd.vv v4, v2, v1
+ vabdu.vv v4, v2, v1
+ vwabdacc.vv v4, v2, v1
+ vwabdaccu.vv v4, v2, v1
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 1c649628390..5b6c01e0f09 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -2248,6 +2248,17 @@
#define MASK_VSM3C_VI 0xfe00707f
#define MATCH_VSM3ME_VV 0x82002077
#define MASK_VSM3ME_VV 0xfe00707f
+/* Zvabd instructions. */
+#define MATCH_VABS_V 0x48082057
+#define MASK_VABS_V 0xfc0ff07f
+#define MATCH_VABD_VV 0x44002057
+#define MASK_VABD_VV 0xfc00707f
+#define MATCH_VABDU_VV 0x4c002057
+#define MASK_VABDU_VV 0xfc00707f
+#define MATCH_VWABDACC_VV 0x54002057
+#define MASK_VWABDACC_VV 0xfc00707f
+#define MATCH_VWABDACCU_VV 0x58002057
+#define MASK_VWABDACCU_VV 0xfc00707f
/* Zcb instructions. */
#define MATCH_C_LBU 0x8000
#define MASK_C_LBU 0xfc03
diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h
index 858fcce6871..8b7840f49d7 100644
--- a/include/opcode/riscv.h
+++ b/include/opcode/riscv.h
@@ -552,6 +552,7 @@ enum riscv_insn_class
INSN_CLASS_ZVKNHA_OR_ZVKNHB,
INSN_CLASS_ZVKSED,
INSN_CLASS_ZVKSH,
+ INSN_CLASS_ZVABD,
INSN_CLASS_ZICFISS,
INSN_CLASS_ZICFISS_AND_ZCMOP,
INSN_CLASS_ZICFILP,
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index b34fffed471..6867a8ac2c7 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -2260,6 +2260,13 @@ const struct riscv_opcode riscv_opcodes[] =
{"vsm3c.vi", 0, INSN_CLASS_ZVKSH, "Vd,Vt,Vj", MATCH_VSM3C_VI, MASK_VSM3C_VI, match_opcode, 0},
{"vsm3me.vv", 0, INSN_CLASS_ZVKSH, "Vd,Vt,Vs", MATCH_VSM3ME_VV, MASK_VSM3ME_VV, match_opcode, 0},
+/* Zvabd instructions. */
+{"vabs.v", 0, INSN_CLASS_ZVABD, "Vd,VtVm", MATCH_VABS_V, MASK_VABS_V, match_opcode, 0},
+{"vabd.vv", 0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VABD_VV, MASK_VABD_VV, match_opcode, 0},
+{"vabdu.vv", 0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VABDU_VV, MASK_VABDU_VV, match_opcode, 0},
+{"vwabdacc.vv", 0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VWABDACC_VV, MASK_VWABDACC_VV, match_opcode, 0},
+{"vwabdaccu.vv", 0, INSN_CLASS_ZVABD, "Vd,Vt,VsVm", MATCH_VWABDACCU_VV, MASK_VWABDACCU_VV, match_opcode, 0},
+
/* ZCB instructions. */
{"c.lbu", 0, INSN_CLASS_ZCB, "Ct,Wcb(Cs)", MATCH_C_LBU, MASK_C_LBU, match_opcode, INSN_DREF|INSN_1_BYTE },
{"c.lhu", 0, INSN_CLASS_ZCB, "Ct,Wch(Cs)", MATCH_C_LHU, MASK_C_LHU, match_opcode, INSN_DREF|INSN_2_BYTE },
--
2.43.0
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