[PATCH 0/2] s390: Simplify (dis)assembly of operands with const bits

[Jens Remus]

Am 12.07.2024 um 16:11 schrieb Jens Remus:
> Simplify the s390 assembler and disassembler logic for processing of
> instruction operands with constant bits.
> 
> Patch 1 removes the need for the operand flags OR1, OR2, and OR8 to OR
> the respective constant value into the operand during assembly and mask
> it during disassembly. The constant bits are already contained in the
> insn template and can be used from there for both purposes.
> 
> Patch 2 relaxes the operand constraints of the extended mnemonics
> risbg[n]z, risb{h|l}gz, and {rns|ros|rxs}bgt. Out of the I3, I4, and I5
> operands only the I3/I4 operand containing the Z/T-bit was restricted
> to the exact 6/5-bit width. All other instructions only adhere to the
> instruction format operand constraints. This aligns GNU Assembler to
> the LLVM Assembler on s390x and removes the operands U5 and U6.

...

> Jens Remus (2):
>    s390: Simplify (dis)assembly of insn operands with const bits
>    s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand
>      constraints

Commited to mainline with Andreas' approval.

Regards,
Jens
-- 
Jens Remus
Linux on Z Development (D3303) and z/VSE Support
+49-7031-16-1128 Office
jremus@de.ibm.com

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