[PATCH] Support Intel AVX10.2 media instructions

[Jiang, Haochen]

> From: Jan Beulich <jbeulich@suse.com>
> Sent: Friday, August 30, 2024 8:53 PM
> 
> On 29.08.2024 09:16, Haochen Jiang wrote:
> > --- /dev/null
> > +++ b/gas/testsuite/gas/i386/avx10_2-256-1.s
> > @@ -0,0 +1,140 @@
> > +# Check 32bit AVX10.2/256 instructions
> > +
> > +	.arch generic32
> > +	.arch .avx10.2/256
> > +	.text
> > +_start:
> > +	.irp m, ss, su, uu
> > +	vpdpb\m\()d	%ymm4, %ymm5, %ymm6{%k7}
> > +	vpdpb\m\()d	%xmm4, %xmm5, %xmm6{%k7}
> > +	vpdpb\m\()d	0x10000000(%esp, %esi, 8), %ymm5, %ymm6{%k7}
> > +	vpdpb\m\()d	(%ecx){1to8}, %ymm5, %ymm6
> > +	vpdpb\m\()d	4064(%ecx), %ymm5, %ymm6{%k7}
> > +	vpdpb\m\()d	-512(%edx){1to8}, %ymm5, %ymm6{%k7}{z}
> > +	vpdpb\m\()d	0x10000000(%esp, %esi, 8), %xmm5, %xmm6{%k7}
> > +	vpdpb\m\()d	(%ecx){1to4}, %xmm5, %xmm6
> > +	vpdpb\m\()d	2032(%ecx), %xmm5, %xmm6{%k7}
> > +	vpdpb\m\()d	-512(%edx){1to4}, %xmm5, %xmm6{%k7}{z}
> > +	vpdpb\m\()ds	%ymm4, %ymm5, %ymm6{%k7}
> > +	vpdpb\m\()ds	%xmm4, %xmm5, %xmm6{%k7}
> > +	vpdpb\m\()ds	0x10000000(%esp, %esi, 8), %ymm5, %ymm6{%k7}
> > +	vpdpb\m\()ds	(%ecx){1to8}, %ymm5, %ymm6
> > +	vpdpb\m\()ds	4064(%ecx), %ymm5, %ymm6{%k7}
> > +	vpdpb\m\()ds	-512(%edx){1to8}, %ymm5, %ymm6{%k7}{z}
> > +	vpdpb\m\()ds	0x10000000(%esp, %esi, 8), %xmm5, %xmm6{%k7}
> > +	vpdpb\m\()ds	(%ecx){1to4}, %xmm5, %xmm6
> > +	vpdpb\m\()ds	2032(%ecx), %xmm5, %xmm6{%k7}
> > +	vpdpb\m\()ds	-512(%edx){1to4}, %xmm5, %xmm6{%k7}{z}
> > +	.endr
> 
> The 2nd half is fully redundant with the 1st, except for the trailing s.
> Use a 2nd, nested .irp?

I am not sure if it could be done with .irp, n, ,s or something similar.
I will have a try.

> 
> > +	.irp m, su, us, uu
> > +	vpdpw\m\()d	%ymm4, %ymm5, %ymm6{%k7}
> > +	vpdpw\m\()d	%xmm4, %xmm5, %xmm6{%k7}
> > +	vpdpw\m\()d	0x10000000(%esp, %esi, 8), %ymm5, %ymm6{%k7}
> > +	vpdpw\m\()d	(%ecx){1to8}, %ymm5, %ymm6
> > +	vpdpw\m\()d	4064(%ecx), %ymm5, %ymm6{%k7}
> > +	vpdpw\m\()d	-512(%edx){1to8}, %ymm5, %ymm6{%k7}{z}
> > +	vpdpw\m\()d	0x10000000(%esp, %esi, 8), %xmm5, %xmm6{%k7}
> > +	vpdpw\m\()d	(%ecx){1to4}, %xmm5, %xmm6
> > +	vpdpw\m\()d	2032(%ecx), %xmm5, %xmm6{%k7}
> > +	vpdpw\m\()d	-512(%edx){1to4}, %xmm5, %xmm6{%k7}{z}
> > +	vpdpw\m\()ds	%ymm4, %ymm5, %ymm6{%k7}
> > +	vpdpw\m\()ds	%xmm4, %xmm5, %xmm6{%k7}
> > +	vpdpw\m\()ds	0x10000000(%esp, %esi, 8), %ymm5, %ymm6{%k7}
> > +	vpdpw\m\()ds	(%ecx){1to8}, %ymm5, %ymm6
> > +	vpdpw\m\()ds	4064(%ecx), %ymm5, %ymm6{%k7}
> > +	vpdpw\m\()ds	-512(%edx){1to8}, %ymm5, %ymm6{%k7}{z}
> > +	vpdpw\m\()ds	0x10000000(%esp, %esi, 8), %xmm5, %xmm6{%k7}
> > +	vpdpw\m\()ds	(%ecx){1to4}, %xmm5, %xmm6
> > +	vpdpw\m\()ds	2032(%ecx), %xmm5, %xmm6{%k7}
> > +	vpdpw\m\()ds	-512(%edx){1to4}, %xmm5, %xmm6{%k7}{z}
> > +	.endr
> > +
> > +	vdpphps	%ymm4, %ymm5, %ymm6{%k7}
> > +	vdpphps	%xmm4, %xmm5, %xmm6{%k7}
> > +	vdpphps	0x10000000(%esp, %esi, 8), %ymm5, %ymm6{%k7}
> > +	vdpphps	(%ecx){1to8}, %ymm5, %ymm6
> > +	vdpphps	4064(%ecx), %ymm5, %ymm6{%k7}
> 
> Blank line between the blocks?

I intentionally do that to make it clearer. We could remove that.

> 
> > --- a/opcodes/i386-dis-evex-prefix.h
> > +++ b/opcodes/i386-dis-evex-prefix.h
> > @@ -231,8 +231,8 @@
> >    },
> >    /* PREFIX_EVEX_0F3852 */
> >    {
> > -    { Bad_Opcode },
> > -    { "vdpbf16p%XS", { XM, Vex, EXx }, 0 },
> > +    { "vdpphp%XS",	{ XM, Vex, EXx, EXxEVexR }, 0 },
> 
> In the description you validly say no rounding is involved here. Why the
> EXxEVexR?

Ah... It is definitely a misstep when moving everything around or the ISA
evolves, should be removed.

> 
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -3103,6 +3103,25 @@ vpdpwsuds, 0xf3d3, AVX_VNNI_INT16,
> Modrm|Vex|Space0F38|Src1VVVV|VexW0|CheckOpera
> >
> >  // AVX-VNNI-INT16 instructions end.
> >
> > +// AVX10.2 media instructions.
> > +
> > +vdpphps, 0x52, AVX10_2,
> Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|Ch
> eckOperandSize|NoSuf,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +vmpsadbw, 0xf342, AVX10_2,
> Modrm|Masking|Space0F3A|Src1VVVV|VexW0|Disp8ShiftVL|CheckOperan
> dSize|NoSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +vpdpbuud, 0x50, AVX10_2,
> Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|Ch
> eckOperandSize|NoSuf,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +vpdpbuuds, 0x51, AVX10_2,
> Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|Ch
> eckOperandSize|NoSuf,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +vpdpbssd, 0xf250, AVX10_2,
> Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|Ch
> eckOperandSize|NoSuf,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +vpdpbssds, 0xf251, AVX10_2,
> Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|Ch
> eckOperandSize|NoSuf,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +vpdpbsud, 0xf350, AVX10_2,
> Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|Ch
> eckOperandSize|NoSuf,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +vpdpbsuds, 0xf351, AVX10_2,
> Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|Ch
> eckOperandSize|NoSuf,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +vpdpwuud, 0xd2, AVX10_2,
> Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|Ch
> eckOperandSize|NoSuf,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +vpdpwuuds, 0xd3, AVX10_2,
> Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|Ch
> eckOperandSize|NoSuf,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +vpdpwusd, 0x66d2, AVX10_2,
> Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|Ch
> eckOperandSize|NoSuf,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +vpdpwusds, 0x66d3, AVX10_2,
> Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|Ch
> eckOperandSize|NoSuf,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +vpdpwsud, 0xf3d2, AVX10_2,
> Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|Ch
> eckOperandSize|NoSuf,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +vpdpwsuds, 0xf3d3, AVX10_2,
> Modrm|Space0F38|Src1VVVV|Masking|VexW0|Broadcast|Disp8ShiftVL|Ch
> eckOperandSize|NoSuf,
> { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex,
> RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM }
> > +
> > +// AVX10.2 media instructions end.
> 
> This will want re-basing over the templatization patch I sent earlier in
> the day. The resulting diff for this file will be quite a bit smaller then.

Sure. I will wait for your patch check-in. Thank for that refactor.

> 
> Jan