[PATCH 6/6] Support Intel AMX-MOVRS

[Jiang, Haochen]

> From: Jan Beulich <jbeulich@suse.com>
> Sent: Monday, November 18, 2024 11:39 PM
> To: Jiang, Haochen <haochen.jiang@intel.com>; Hu, Lin1 <lin1.hu@intel.com>
> Cc: binutils@sourceware.org; H.J. Lu <hjl.tools@gmail.com>
> Subject: Re: [PATCH 6/6] Support Intel AMX-MOVRS
>  
> > --- a/opcodes/i386-opc.tbl
> > +++ b/opcodes/i386-opc.tbl
> > @@ -3197,6 +3197,11 @@ t2rpntlvwz0t1, 0x6f, AMX_TRANSPOSE,
> > TMMPairOperand1|Sibmem|Vex128|Space0F38|VexW
> >  t2rpntlvwz1, 0x666e, AMX_TRANSPOSE,
> > TMMPairOperand1|Sibmem|Vex128|Space0F38|VexW0|NoSuf, {
> > Unspecified|BaseIndex, RegTMM }  t2rpntlvwz1t1, 0x666f,
> AMX_TRANSPOSE,
> > TMMPairOperand1|Sibmem|Vex128|Space0F38|VexW0|NoSuf, {
> > Unspecified|BaseIndex, RegTMM }
> >
> > +t2rpntlvwz0rs, 0xf8, AMX_MOVRS&AMX_TRANSPOSE,
> > +TMMPairOperand1|Sibmem|Vex128|xVexMap5|VexW0|NoSuf, {
> > +Unspecified|BaseIndex, RegTMM } t2rpntlvwz0rst1, 0xf9,
> > +AMX_MOVRS&AMX_TRANSPOSE,
> > +TMMPairOperand1|Sibmem|Vex128|xVexMap5|VexW0|NoSuf, {
> > +Unspecified|BaseIndex, RegTMM } t2rpntlvwz1rs, 0x66f8,
> > +AMX_MOVRS&AMX_TRANSPOSE,
> > +TMMPairOperand1|Sibmem|Vex128|xVexMap5|VexW0|NoSuf, {
> > +Unspecified|BaseIndex, RegTMM } t2rpntlvwz1rst1, 0x66f9,
> > +AMX_MOVRS&AMX_TRANSPOSE,
> > +TMMPairOperand1|Sibmem|Vex128|xVexMap5|VexW0|NoSuf, {
> > +Unspecified|BaseIndex, RegTMM }
> 
> Judging from VMOVRS{B,W,D,Q}, shouldn't the RS infix move a little earlier,
> ahead of the element width specifier: T2RPNTLVRSW{Z0,Z1}{,T1}?
> ...
> Same here: TILELOADRSD{,T1} would seem like a better match for
> VMOVRS{B,W,D,Q}.

Per my understanding, D is the element size in tile, while RS hint is for whole
tile, not for the elements in tile. That is why RS will not appear before D.

Thx,
Haochen