[PATCH 6/6] Support Intel AMX-MOVRS

[Jan Beulich]

On 13.11.2024 09:44, Haochen Jiang wrote:
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-amx-movrs-inval.l
> @@ -0,0 +1,5 @@
> +.* Assembler messages:
> +.*:6: Error: `t2rpntlvwz0rs' is not supported on `x86_64.noamx_transpose'
> +.*:7: Error: `t2rpntlvwz0rst1' is not supported on `x86_64.noamx_transpose'
> +.*:8: Error: `t2rpntlvwz1rs' is not supported on `x86_64.noamx_transpose'
> +.*:9: Error: `t2rpntlvwz1rst1' is not supported on `x86_64.noamx_transpose'
> --- /dev/null
> +++ b/gas/testsuite/gas/i386/x86-64-amx-movrs-inval.s
> @@ -0,0 +1,9 @@
> +# Check Invalid 64bit AMX-MOVRS instructions
> +
> +	.text
> +	.arch .noamx_transpose
> +_start:
> +	t2rpntlvwz0rs	(%r9), %tmm3
> +	t2rpntlvwz0rst1	(%r9), %tmm3
> +	t2rpntlvwz1rs	(%r9), %tmm3
> +	t2rpntlvwz1rst1	(%r9), %tmm3

This is too little imo - the SIBMEM constraints also want checking.

> --- a/opcodes/i386-opc.tbl
> +++ b/opcodes/i386-opc.tbl
> @@ -3197,6 +3197,11 @@ t2rpntlvwz0t1, 0x6f, AMX_TRANSPOSE, TMMPairOperand1|Sibmem|Vex128|Space0F38|VexW
>  t2rpntlvwz1, 0x666e, AMX_TRANSPOSE, TMMPairOperand1|Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
>  t2rpntlvwz1t1, 0x666f, AMX_TRANSPOSE, TMMPairOperand1|Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
>  
> +t2rpntlvwz0rs, 0xf8, AMX_MOVRS&AMX_TRANSPOSE, TMMPairOperand1|Sibmem|Vex128|xVexMap5|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
> +t2rpntlvwz0rst1, 0xf9, AMX_MOVRS&AMX_TRANSPOSE, TMMPairOperand1|Sibmem|Vex128|xVexMap5|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
> +t2rpntlvwz1rs, 0x66f8, AMX_MOVRS&AMX_TRANSPOSE, TMMPairOperand1|Sibmem|Vex128|xVexMap5|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
> +t2rpntlvwz1rst1, 0x66f9, AMX_MOVRS&AMX_TRANSPOSE, TMMPairOperand1|Sibmem|Vex128|xVexMap5|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }

Judging from VMOVRS{B,W,D,Q}, shouldn't the RS infix move a little earlier,
ahead of the element width specifier: T2RPNTLVRSW{Z0,Z1}{,T1}?

> @@ -3230,6 +3235,8 @@ tdphf8ps, 0x66fd, AMX_FP8, Modrm|Vex128|xVexMap5|Src2VVVV|VexW0|NoSuf, { RegTMM,
>  
>  tileloadd, 0xf24b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
>  tileloaddt1, 0x664b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
> +tileloaddrs, 0xf24a, AMX_MOVRS, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
> +tileloaddrst1, 0x664a, AMX_MOVRS, Sibmem|Vex128|Space0F38|VexW0|NoSuf, { Unspecified|BaseIndex, RegTMM }
>  tilemovrow, 0x664a, AMX_AVX512, Modrm|EVex512|Space0F38|Src2VVVV|VexW0|NoSuf, { Reg32, RegTMM, RegZMM }
>  tilemovrow, 0x6607, AMX_AVX512, Modrm|EVex512|Space0F3A|VexW0|NoSuf, { Imm8, RegTMM, RegZMM }
>  tilestored, 0xf34b, APX_F(AMX_TILE), Sibmem|Vex128|EVex128|Space0F38|VexW0|NoSuf, { RegTMM, Unspecified|BaseIndex }

Same here: TILELOADRSD{,T1} would seem like a better match for VMOVRS{B,W,D,Q}.

For all of these: What about their APX forms (presumably simply re-encoded as
EVEX at the same position in the opcode map)?

Jan