[PATCH] PowerPC: Add support for RFC02657 - AES acceleration, instructions

[Jan Beulich]

On 18.12.2024 14:26, Surya Kumari Jangala wrote:
> @@ -9389,6 +9444,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>  {"xsnegdp",	XX2(60,377),	XX2_MASK,    PPCVSX,	PPCVLE,		{XT6, XB6}},
>  {"xvmaxsp",	XX3(60,192),	XX3_MASK,    PPCVSX,	PPCVLE,		{XT6, XA6, XB6}},
>  {"xvnmaddasp",	XX3(60,193),	XX3_MASK,    PPCVSX,	PPCVLE,		{XT6, XA6, XB6}},
> +
> +{"xxaes128encp",XX3M(60,194,0,0),XX3AESM_MASK,  PPCVSX,	PPCVLE|EXT,	{XTP, XA5p, XB5p}},
> +{"xxaes192encp",XX3M(60,194,0,1),XX3AESM_MASK,  PPCVSX,	PPCVLE|EXT,	{XTP, XA5p, XB5p}},
> +{"xxaes256encp",XX3M(60,194,1,0),XX3AESM_MASK,  PPCVSX,	PPCVLE|EXT,	{XTP, XA5p, XB5p}},
> +{"xxaesencp",	XX3M(60,194,0,0),XX3AES_MASK,   PPCVSX,	PPCVLE,		{XTP, XA5p, XB5p, AESM}},
> +{"xxaes128decp",XX3M(60,202,0,0),XX3AESM_MASK,  PPCVSX,	PPCVLE|EXT,	{XTP, XA5p, XB5p}},
> +{"xxaes192decp",XX3M(60,202,0,1),XX3AESM_MASK,  PPCVSX,	PPCVLE|EXT,	{XTP, XA5p, XB5p}},
> +{"xxaes256decp",XX3M(60,202,1,0),XX3AESM_MASK,  PPCVSX,	PPCVLE|EXT,	{XTP, XA5p, XB5p}},
> +{"xxaesdecp",	XX3M(60,202,0,0),XX3AES_MASK,   PPCVSX,	PPCVLE,		{XTP, XA5p, XB5p, AESM}},
> +
>  {"xvcvspuxds",	XX2(60,392),	XX2_MASK,    PPCVSX,	PPCVLE,		{XT6, XB6}},
>  {"xvcvdpsp",	XX2(60,393),	XX2_MASK,    PPCVSX,	PPCVLE,		{XT6, XB6}},
>  {"xvminsp",	XX3(60,200),	XX3_MASK,    PPCVSX,	PPCVLE,		{XT6, XA6, XB6}},
> @@ -9398,11 +9463,22 @@ const struct powerpc_opcode powerpc_opcodes[] = {
>  {"xvmovsp",	XX3(60,208),	XX3_MASK,    PPCVSX,	PPCVLE|EXT,	{XT6, XAB6}},
>  {"xvcpsgnsp",	XX3(60,208),	XX3_MASK,    PPCVSX,	PPCVLE,		{XT6, XA6, XB6}},
>  {"xvnmsubasp",	XX3(60,209),	XX3_MASK,    PPCVSX,	PPCVLE,		{XT6, XA6, XB6}},
> +
> +{"xxaes128genlkp",XX2M(60,420,0,0),XX2AESM_MASK, PPCVSX, PPCVLE|EXT,	{XTP, XB5p}},
> +{"xxaes192genlkp",XX2M(60,420,0,1),XX2AESM_MASK, PPCVSX, PPCVLE|EXT,	{XTP, XB5p}},
> +{"xxaes256genlkp",XX2M(60,420,1,0),XX2AESM_MASK, PPCVSX, PPCVLE|EXT,	{XTP, XB5p}},
> +{"xxaesgenlkp",   XX2M(60,420,0,0),XX2AES_MASK,  PPCVSX, PPCVLE,	{XTP, XB5p, AESM}},
> +
>  {"xvcvuxdsp",	XX2(60,424),	XX2_MASK,    PPCVSX,	PPCVLE,		{XT6, XB6}},
>  {"xvnabssp",	XX2(60,425),	XX2_MASK,    PPCVSX,	PPCVLE,		{XT6, XB6}},
>  {"xvtstdcsp",	XX2(60,426),  XX2DCMXS_MASK, PPCVSX3,	PPCVLE,		{XT6, XB6, DCMXS}},
>  {"xviexpsp",	XX3(60,216),	XX3_MASK,    PPCVSX3,	PPCVLE,		{XT6, XA6, XB6}},
>  {"xvnmsubmsp",	XX3(60,217),	XX3_MASK,    PPCVSX,	PPCVLE,		{XT6, XA6, XB6}},
> +
> +{"xxgfmul128gcm",XX3GF(60,26,3,0),  XX3GFP_MASK, PPCVSX,	PPCVLE|EXT,	{XT6, XA6, XB6}},
> +{"xxgfmul128xts",XX3GF(60,26,3,1),  XX3GFP_MASK, PPCVSX,	PPCVLE|EXT,	{XT6, XA6, XB6}},
> +{"xxgfmul128",	 XX3GF(60,26,3,0),  XX3GF_MASK,  PPCVSX,	PPCVLE,		{XT6, XA6, XB6, P}},

Shouldn't all of these additions be PPCVSXF, like the RFC02677 and RFC02680
had it?

Jan