[PATCH] PowerPC: Add support for RFC02657 - AES acceleration, instructions
Surya Kumari Jangala
jskumari@linux.ibm.com
Wed Dec 18 13:26:23 GMT 2024
PowerPC: Add support for RFC02657 - AES acceleration instructions
opcodes/
* ppc-opc.c (insert_m, extract_m): New functions.
(AESM, P, XX2M, XX3M, XX3GF, XX2AES_MASK, XX2AESM_MASK,
XX3AES_MASK, XX3AESM_MASK, XX3GF_MASK, XX3GFP_MASK): New macros.
(UIM): Update for new macros.
(powerpc_opcodes): Add xxaes128encp, xxaes192encp, xxaes256encp,
xxaesencp, xxaes128decp, xxaes192decp, xxaes256decp, xxaesdecp,
xxaes128genlkp, xxaes192genlkp, xxaes256genlkp, xxaesgenlkp,
xxgfmul128gcm, xxgfmul128xts, xxgfmul128.
gas/
* testsuite/gas/ppc/future.s: New test.
* testsuite/gas/ppc/future.d: Likewise.
---
gas/testsuite/gas/ppc/future.d | 22 ++++++++++
gas/testsuite/gas/ppc/future.s | 22 ++++++++++
opcodes/ppc-opc.c | 78 +++++++++++++++++++++++++++++++++-
3 files changed, 121 insertions(+), 1 deletion(-)
diff --git a/gas/testsuite/gas/ppc/future.d b/gas/testsuite/gas/ppc/future.d
index d639e8c618f..76a30a50316 100644
--- a/gas/testsuite/gas/ppc/future.d
+++ b/gas/testsuite/gas/ppc/future.d
@@ -35,4 +35,26 @@ Disassembly of section \.text:
.*: (d8 1d 22 f0|f0 22 1d d8) xvmulhsh vs1,vs2,vs3
.*: (90 b3 95 f2|f2 95 b3 90) xvmulhuw vs20,vs21,vs22
.*: (d6 a3 8a f2|f2 8a a3 d6) xvmulhuh vs20,vs42,vs52
+.*: (10 36 44 f0|f0 44 36 10) xxaes128encp vs2,vs4,vs6
+.*: (10 36 44 f0|f0 44 36 10) xxaes128encp vs2,vs4,vs6
+.*: (12 2e 44 f0|f0 44 2e 12) xxaes192encp vs2,vs4,vs36
+.*: (12 2e 44 f0|f0 44 2e 12) xxaes192encp vs2,vs4,vs36
+.*: (16 26 23 f0|f0 23 26 16) xxaes256encp vs32,vs34,vs36
+.*: (16 26 23 f0|f0 23 26 16) xxaes256encp vs32,vs34,vs36
+.*: (50 36 44 f0|f0 44 36 50) xxaes128decp vs2,vs4,vs6
+.*: (50 36 44 f0|f0 44 36 50) xxaes128decp vs2,vs4,vs6
+.*: (52 2e 44 f0|f0 44 2e 52) xxaes192decp vs2,vs4,vs36
+.*: (52 2e 44 f0|f0 44 2e 52) xxaes192decp vs2,vs4,vs36
+.*: (56 26 23 f0|f0 23 26 56) xxaes256decp vs32,vs34,vs36
+.*: (56 26 23 f0|f0 23 26 56) xxaes256decp vs32,vs34,vs36
+.*: (90 96 00 f2|f2 00 96 90) xxaes128genlkp vs16,vs18
+.*: (90 96 00 f2|f2 00 96 90) xxaes128genlkp vs16,vs18
+.*: (92 9e 20 f1|f1 20 9e 92) xxaes192genlkp vs40,vs50
+.*: (92 9e 20 f1|f1 20 9e 92) xxaes192genlkp vs40,vs50
+.*: (92 b6 81 f2|f2 81 b6 92) xxaes256genlkp vs20,vs54
+.*: (92 b6 81 f2|f2 81 b6 92) xxaes256genlkp vs20,vs54
+.*: (d0 1e 22 f0|f0 22 1e d0) xxgfmul128gcm vs1,vs2,vs3
+.*: (d0 1e 22 f0|f0 22 1e d0) xxgfmul128gcm vs1,vs2,vs3
+.*: (d6 0f e0 f3|f3 e0 0f d6) xxgfmul128xts vs31,vs32,vs33
+.*: (d6 0f e0 f3|f3 e0 0f d6) xxgfmul128xts vs31,vs32,vs33
#pass
diff --git a/gas/testsuite/gas/ppc/future.s b/gas/testsuite/gas/ppc/future.s
index 9abf6b3de7b..fec99e348bf 100644
--- a/gas/testsuite/gas/ppc/future.s
+++ b/gas/testsuite/gas/ppc/future.s
@@ -27,3 +27,25 @@ _start:
xvmulhsh 1,2,3
xvmulhuw 20,21,22
xvmulhuh 20,42,52
+ xxaesencp 2, 4, 6, 0
+ xxaes128encp 2, 4, 6
+ xxaesencp 2, 4, 36, 1
+ xxaes192encp 2, 4, 36
+ xxaesencp 32, 34, 36, 2
+ xxaes256encp 32, 34, 36
+ xxaesdecp 2, 4, 6, 0
+ xxaes128decp 2, 4, 6
+ xxaesdecp 2, 4, 36, 1
+ xxaes192decp 2, 4, 36
+ xxaesdecp 32, 34, 36, 2
+ xxaes256decp 32, 34, 36
+ xxaesgenlkp 16, 18, 0
+ xxaes128genlkp 16, 18
+ xxaesgenlkp 40, 50, 1
+ xxaes192genlkp 40, 50
+ xxaesgenlkp 20, 54, 2
+ xxaes256genlkp 20, 54
+ xxgfmul128 1, 2, 3, 0
+ xxgfmul128gcm 1, 2, 3
+ xxgfmul128 31, 32, 33, 1
+ xxgfmul128xts 31, 32, 33
diff --git a/opcodes/ppc-opc.c b/opcodes/ppc-opc.c
index 568a3d6d8f0..fabf56a2526 100644
--- a/opcodes/ppc-opc.c
+++ b/opcodes/ppc-opc.c
@@ -2392,6 +2392,28 @@ extract_dm (uint64_t insn,
return (value) ? 1 : 0;
}
+static uint64_t
+insert_m (uint64_t insn,
+ int64_t value,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ const char **errmsg)
+{
+ if (value!= 0 && value != 1 && value != 2)
+ *errmsg = _("invalid M value");
+ return insn | ((value & 0x2) << (16 - 1)) | ((value & 0x1) << 11);
+}
+
+static int64_t
+extract_m (uint64_t insn,
+ ppc_cpu_t dialect ATTRIBUTE_UNUSED,
+ int *invalid)
+{
+ int64_t value = ((insn >> 11) & 1) | ((insn >> 15) & 2);
+ if (value != 0 && value != 1 && value != 2)
+ *invalid = 1;
+ return value;
+}
+
/* The VLESIMM field in an I16A form instruction. This is split. */
static uint64_t
@@ -3887,8 +3909,12 @@ const struct powerpc_operand powerpc_operands[] =
#define DMEX DM + 1
{ 0x3, 8, insert_dm, extract_dm, 0 },
+#define AESM DMEX + 1
+ { 0x3, PPC_OPSHIFT_INV, insert_m, extract_m, 0 },
+
+
/* The UIM field in an XX2 form instruction. */
-#define UIM DMEX + 1
+#define UIM AESM + 1
/* The 2-bit UIMM field in a VX form instruction. */
#define UIMM2 UIM
/* The 2-bit L field in a darn instruction. */
@@ -3943,6 +3969,8 @@ const struct powerpc_operand powerpc_operands[] =
#define ms vs + 1
#define yx ms
+ /* The P field in Galois Field XX3 form instruction. */
+#define P yx
{ 0x1, 8, NULL, NULL, 0 },
#define SVLcr ms + 1
@@ -4467,6 +4495,12 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
/* A XX2 form instruction with the VA bits specified. */
#define XX2VA(op, xop, vaop) (XX2(op,xop) | (((vaop) & 0x1f) << 16))
+/* An XX2 form instruction with the M bits specified. */
+#define XX2M(op, xop, m0, m1) \
+ (XX2 (op, xop) \
+ | (((uint64_t)(m0) & 1) << 16) \
+ | (((uint64_t)(m1) & 1) << 11))
+
/* An XX3 form instruction. */
#define XX3(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0xff) << 3))
@@ -4476,6 +4510,16 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
| (((uint64_t)(rc) & 1) << 10) \
| ((((uint64_t)(xop)) & 0x7f) << 3))
+#define XX3M(op, xop, m0, m1) \
+ (XX3 (op, xop) \
+ | (((uint64_t)(m0) & 1) << 16) \
+ | (((uint64_t)(m1) & 1) << 11))
+
+#define XX3GF(op, xop, xop1, p) \
+ (XX3 (op, xop) \
+ | (((uint64_t)(xop1) & 3) << 9) \
+ | (((uint64_t)(p) & 1) << 8))
+
/* An XX4 form instruction. */
#define XX4(op, xop) (OP (op) | ((((uint64_t)(xop)) & 0x3) << 4))
@@ -4565,6 +4609,17 @@ const unsigned int num_powerpc_operands = ARRAY_SIZE (powerpc_operands);
#define XX2DMR_MASK (XX2ACC_MASK | (0xf << 17))
#define XX3GERX_MASK (XX3ACC_MASK | (1 << 16))
+/* The masks for XX2 AES instructions with m0, m1 bits. */
+#define XX2AES_MASK (XX2M (0x3f, 0x1ff, 0, 0) | (0xf << 17) | 1)
+#define XX2AESM_MASK (XX2AES_MASK | (1 << 16) | (1 << 11))
+
+/* The masks for XX3 AES instructions with m0, m1 bits. */
+#define XX3AES_MASK (XX3M (0x3f, 0xff, 0, 0) | 1)
+#define XX3AESM_MASK (XX3AES_MASK | (1 << 16) | (1 << 11))
+
+#define XX3GF_MASK (XX3 (0x3f, 0x1f) | (3 << 9))
+#define XX3GFP_MASK (XX3GF_MASK | (1 << 8))
+
/* The mask for an XX4 form instruction. */
#define XX4_MASK XX4 (0x3f, 0x3)
@@ -9389,6 +9444,16 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"xsnegdp", XX2(60,377), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
{"xvmaxsp", XX3(60,192), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
{"xvnmaddasp", XX3(60,193), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
+
+{"xxaes128encp",XX3M(60,194,0,0),XX3AESM_MASK, PPCVSX, PPCVLE|EXT, {XTP, XA5p, XB5p}},
+{"xxaes192encp",XX3M(60,194,0,1),XX3AESM_MASK, PPCVSX, PPCVLE|EXT, {XTP, XA5p, XB5p}},
+{"xxaes256encp",XX3M(60,194,1,0),XX3AESM_MASK, PPCVSX, PPCVLE|EXT, {XTP, XA5p, XB5p}},
+{"xxaesencp", XX3M(60,194,0,0),XX3AES_MASK, PPCVSX, PPCVLE, {XTP, XA5p, XB5p, AESM}},
+{"xxaes128decp",XX3M(60,202,0,0),XX3AESM_MASK, PPCVSX, PPCVLE|EXT, {XTP, XA5p, XB5p}},
+{"xxaes192decp",XX3M(60,202,0,1),XX3AESM_MASK, PPCVSX, PPCVLE|EXT, {XTP, XA5p, XB5p}},
+{"xxaes256decp",XX3M(60,202,1,0),XX3AESM_MASK, PPCVSX, PPCVLE|EXT, {XTP, XA5p, XB5p}},
+{"xxaesdecp", XX3M(60,202,0,0),XX3AES_MASK, PPCVSX, PPCVLE, {XTP, XA5p, XB5p, AESM}},
+
{"xvcvspuxds", XX2(60,392), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
{"xvcvdpsp", XX2(60,393), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
{"xvminsp", XX3(60,200), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
@@ -9398,11 +9463,22 @@ const struct powerpc_opcode powerpc_opcodes[] = {
{"xvmovsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE|EXT, {XT6, XAB6}},
{"xvcpsgnsp", XX3(60,208), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
{"xvnmsubasp", XX3(60,209), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
+
+{"xxaes128genlkp",XX2M(60,420,0,0),XX2AESM_MASK, PPCVSX, PPCVLE|EXT, {XTP, XB5p}},
+{"xxaes192genlkp",XX2M(60,420,0,1),XX2AESM_MASK, PPCVSX, PPCVLE|EXT, {XTP, XB5p}},
+{"xxaes256genlkp",XX2M(60,420,1,0),XX2AESM_MASK, PPCVSX, PPCVLE|EXT, {XTP, XB5p}},
+{"xxaesgenlkp", XX2M(60,420,0,0),XX2AES_MASK, PPCVSX, PPCVLE, {XTP, XB5p, AESM}},
+
{"xvcvuxdsp", XX2(60,424), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
{"xvnabssp", XX2(60,425), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
{"xvtstdcsp", XX2(60,426), XX2DCMXS_MASK, PPCVSX3, PPCVLE, {XT6, XB6, DCMXS}},
{"xviexpsp", XX3(60,216), XX3_MASK, PPCVSX3, PPCVLE, {XT6, XA6, XB6}},
{"xvnmsubmsp", XX3(60,217), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
+
+{"xxgfmul128gcm",XX3GF(60,26,3,0), XX3GFP_MASK, PPCVSX, PPCVLE|EXT, {XT6, XA6, XB6}},
+{"xxgfmul128xts",XX3GF(60,26,3,1), XX3GFP_MASK, PPCVSX, PPCVLE|EXT, {XT6, XA6, XB6}},
+{"xxgfmul128", XX3GF(60,26,3,0), XX3GF_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6, P}},
+
{"xvcvsxdsp", XX2(60,440), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
{"xvnegsp", XX2(60,441), XX2_MASK, PPCVSX, PPCVLE, {XT6, XB6}},
{"xvmaxdp", XX3(60,224), XX3_MASK, PPCVSX, PPCVLE, {XT6, XA6, XB6}},
--
2.43.5
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