[PATCH] RISC-V: Dump instruction without checking architecture support as usual.

[Nelson Chu]

On Fri, Oct 27, 2023 at 10:17 AM Tsukasa OI <research_trasio@irq.a4lg.com>
wrote:

> On 2023/10/27 9:39, Nelson Chu wrote:
> > Since QEMU have supported -Max option to to enable all normal extensions,
> > the dis-assembler should also add an option, -M,max to do the same thing.
> > For the instruction, which have overlapped encodings like zfinx, will not
> > be considered by the -M,max option.
> >
> > opcodes/
> >       * riscv-dis.c (all_ext): New static boolean.  If set, disassemble
> >       without checking architectire string.
> >       (riscv_disassemble_insn): Likewise.
> >       (parse_riscv_dis_option_without_args): Recognized -M,max option.
> > ---
> >  opcodes/riscv-dis.c | 8 +++++++-
> >  1 file changed, 7 insertions(+), 1 deletion(-)
>
> LGTM.
>
> For overlapped encodings, riscv_opcodes ordering will get more important
> but I don't think this change will "break" anything ("max" should be
> used only when the specific architecture IS NOT important).
>
> I remember I submitted a proposal (long time ago) to add a disassembler
> option to specify custom ISA string for the disassembler (where specific
> architecture IS important) and it might be the time to rework on this
> (because "max" and my past proposal "arch=ARCH" would work as a pair).
>

 Yeah probably it's time to get thi, too.  Since it gives more chances for
users to choose what they want to dump, although they may dump the wrong
results, that's their choice ;)

Thanks
Nelson
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