[PATCH] RISC-V: Dump instruction without checking architecture support as usual.

[Tsukasa OI]

On 2023/10/27 9:39, Nelson Chu wrote:
> Since QEMU have supported -Max option to to enable all normal extensions,
> the dis-assembler should also add an option, -M,max to do the same thing.
> For the instruction, which have overlapped encodings like zfinx, will not
> be considered by the -M,max option.
> 
> opcodes/
> 	* riscv-dis.c (all_ext): New static boolean.  If set, disassemble
> 	without checking architectire string.
> 	(riscv_disassemble_insn): Likewise.
> 	(parse_riscv_dis_option_without_args): Recognized -M,max option.
> ---
>  opcodes/riscv-dis.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)

LGTM.

For overlapped encodings, riscv_opcodes ordering will get more important
but I don't think this change will "break" anything ("max" should be
used only when the specific architecture IS NOT important).

I remember I submitted a proposal (long time ago) to add a disassembler
option to specify custom ISA string for the disassembler (where specific
architecture IS important) and it might be the time to rework on this
(because "max" and my past proposal "arch=ARCH" would work as a pair).

Tsukasa


p.s.

Also looking at your patch, I started to think disassembler options that
would visualize custom instructions (or custom instruction/CSR space)
might be helpful for some reverse engineering needs (the priority is
low, even for me though).