[PATCH v1 1/1] opcodes: microblaze: Fix bit masking bug

[Michael Eager]

On 11/10/23 06:24, Nick Clifton wrote:
> Hi Neal,
> 
>> There is currently a bug in the bit masking for the barrel shift
>> instructions because the bit mask is not including all of the
>> register bits which must be zero.  With this patch, the disassembler
>> can be sure that the 32-bit value is indeed a barrel shift instruction
>> and not a data value in memory.
>>
>> This fix can be verified by assembling and disassembling the following:
>>
>>     .text
>>     .long 0x65005f5f
>>
>> With this patch, the bug is fixed, and the objdump will know that
>> 0x65005f5f is not a barrel shift instruction.
>>
> 
> Approved - please apply.

This patch was applied on 10/19/23.

-- 
Michael Eager