[committed] RISC-V: XVentanaCondops support

[Palmer Dabbelt]

On Wed, 26 Apr 2023 14:16:10 PDT (-0700), Jeff Law wrote:
>
>
> On 4/26/23 15:09, Palmer Dabbelt wrote:
>
>>>
>>> The Veyron V1 processor implements XVentanaCondOps, but not Zicond.
>>> That's simply due to timing.
>>
>> Do you have a link to anything that says this?  I don't think we ever
>> got a hard definition of what the requirements are, just some sort of
>> annocement that the chip is going to be publicly availiable.  There's
>> some stuff on the Ventana website, but it's all sort of vague marketing
>> type stuff.
> The processor was announced back in December at the summit which I
> thought was the requirement that you and Philipp had worked out.

We had the various RISC-V port maintainers and long-term contributors in 
FSF toolchain land (ie, binutils/GCC/glibc) agree on something posted to 
the mailing list.

Philipp and I certainly talked about it, but there's no private 
agreements or anything like that -- it's just what we discuss on the 
mailing lists.  Unfortunately he has along history of misrepresenting 
things, but that's really why we're so careful about making sure that 
all the decisions are talked about on the lists.

> We're still waiting on hardware for bring-up.  But in terms of the
> processor features/ISA, that's immutable at this point (as much as I
> wish that weren't the case).

The idea was to have some sort of timeline around availability of the 
hardware -- essentially the goal is to avoid being stuck supporting 
stuff that doesn't actually make it out of the lab.  I can't find 
anything that actually says that, but then also I'm pretty much allergic 
to chip company marketing material these days so I sort of stay out of 
it ;)

The best I've been able to find is this "Veyron V1 is Highest 
Performance RISC-V Processor running at 3.6GHz in 5nm" [1].  The 
big-ticket ones like an SDK and dev board don't seem to exist anywhere 
outside of press releases, though (there's a github [2], but no SDK).

I know it's kind of pedantic, but we've had a lot of issues in the past 
with RISC-V folks making stuff up and trying to push around upstream.  
I'm not saying you're doing that, you've been around long enough that if 
you say you have a chip I believe you.  The goal is to be fair to 
everyone, though -- essentially the same as what happened for the GCC 
patches.

1: https://www.ventanamicro.com/ventana-introduces-veyron-worlds-first-data-center-class-risc-v-cpu-product-family/
2: https://github.com/ventana-micro-systems