[committed] RISC-V: XVentanaCondops support

[Jeff Law]

On 4/26/23 15:09, Palmer Dabbelt wrote:

>>
>> The Veyron V1 processor implements XVentanaCondOps, but not Zicond.
>> That's simply due to timing.
> 
> Do you have a link to anything that says this?  I don't think we ever 
> got a hard definition of what the requirements are, just some sort of 
> annocement that the chip is going to be publicly availiable.  There's 
> some stuff on the Ventana website, but it's all sort of vague marketing 
> type stuff.
The processor was announced back in December at the summit which I 
thought was the requirement that you and Philipp had worked out.

We're still waiting on hardware for bring-up.  But in terms of the 
processor features/ISA, that's immutable at this point (as much as I 
wish that weren't the case).

jeff