[PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers

[Jeff Law]

On 10/1/22 14:27, Andrew Burgess via Binutils wrote:
> Tsukasa OI via Binutils <binutils@sourceware.org> writes:
>
>> Hello,
>>
>> Surprisingly, I found that no vector registers (v0-v31) are assigned DWARF
>> register numbers.  RISC-V ABIs Specification (riscv-elf-psabi-doc) is not
>> ratified yet but at least frozen.  So, I consider it's stable to upstream
>> it.  According to the documentation, it has register numbers 96 (v0) -
>> 127 (v31).
>>
>> [Changes: v1 -> v2]
>> Remove invented word "VPRs" (at least it has no consistent uses in the
>> RISC-V ecosystem) and replaced with "Vector registers"
>>
>> [Changes: v2 -> v3]
>> Changed reference (v1.0-rc3 -> v1.0-rc4).
>>
>> Tracker on GitHub:
>> <https://github.com/a4lg/binutils-gdb/wiki/riscv_psabi_dwarf_vector_regs>
>>
>> RISC-V ABIs Specification Version 1.0-rc4: Frozen
>> <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4>
>>
>>
>> I also added DWARF register number tests not just for CSRs (existing) and
>> vector registers (I just added), but also for GPRs (0-31) and FPRs
>> (32-63).
> Hi Tsukasa,
>
> I can't approve binutils patches, but as this mentioned RISC-V and
> DWARF, both of which I'm interested in, I took a look :)
>
> Both these patches look good to me.  The register numbers align with the
> spec, and the test makes sense.

Well, that's the key property -- they align with the spec.


I'm also not sure if I can approve for binutils, but if I can, OK for 
the trunk ;-)

Jeff