[PATCH v3 0/2] RISC-V psABI: Assign DWARF register numbers to vector registers

[Andrew Burgess]

Tsukasa OI via Binutils <binutils@sourceware.org> writes:

> Hello,
>
> Surprisingly, I found that no vector registers (v0-v31) are assigned DWARF
> register numbers.  RISC-V ABIs Specification (riscv-elf-psabi-doc) is not
> ratified yet but at least frozen.  So, I consider it's stable to upstream
> it.  According to the documentation, it has register numbers 96 (v0) -
> 127 (v31).
>
> [Changes: v1 -> v2]
> Remove invented word "VPRs" (at least it has no consistent uses in the
> RISC-V ecosystem) and replaced with "Vector registers"
>
> [Changes: v2 -> v3]
> Changed reference (v1.0-rc3 -> v1.0-rc4).
>
> Tracker on GitHub:
> <https://github.com/a4lg/binutils-gdb/wiki/riscv_psabi_dwarf_vector_regs>
>
> RISC-V ABIs Specification Version 1.0-rc4: Frozen
> <https://github.com/riscv-non-isa/riscv-elf-psabi-doc/releases/tag/v1.0-rc4>
>
>
> I also added DWARF register number tests not just for CSRs (existing) and
> vector registers (I just added), but also for GPRs (0-31) and FPRs
> (32-63).

Hi Tsukasa,

I can't approve binutils patches, but as this mentioned RISC-V and
DWARF, both of which I'm interested in, I took a look :)

Both these patches look good to me.  The register numbers align with the
spec, and the test makes sense.

Thanks for the patch.

Andrew


>
>
> Thanks,
> Tsukasa
>
>
>
>
> Tsukasa OI (2):
>   RISC-V: Assign DWARF numbers to vector registers
>   RISC-V: Add testcase for DWARF register numbers
>
>  binutils/dwarf.c                     |  28 ++--
>  gas/config/tc-riscv.c                |   3 +
>  gas/testsuite/gas/riscv/dw-regnums.d | 180 ++++++++++++++++++++++++++
>  gas/testsuite/gas/riscv/dw-regnums.s | 184 +++++++++++++++++++++++++++
>  4 files changed, 385 insertions(+), 10 deletions(-)
>  create mode 100644 gas/testsuite/gas/riscv/dw-regnums.d
>  create mode 100644 gas/testsuite/gas/riscv/dw-regnums.s
>
>
> base-commit: 90eca7111355e4c6683c1ab10fd07107ea10f6d1
> -- 
> 2.34.1