[RFC PATCH 0/3] RISC-V: Check shift amount against XLEN (disassembler)

[Tsukasa OI]

This patchset is officially withdrawn as I will submit new simpler
patchset for the exact same issue.

Thanks,
Tsukasa

On 2022/05/23 19:06, Tsukasa OI wrote:
> ** Note **
> This patch is not compatible with my previous Zfinx fixes.  Actual PATCH
> v1 is going to be submitted after this patchset is reviewed and Zfinx
> fixes (relatively high priority) are applied.
> 
> Certain shift instructions have a constraint: shift amount must be less
> than current XLEN.  This constraint is checked on assembler and
> simulator, but not on disassembler.  It causes GDB to print wrong (and
> invalid) instructions and can be a problem while ... for instance,
> checking for invalid build configuration.
> 
> We have several methods to deal with it:
> 
> -   Add `xlen' argument to match_func to test XLEN
> -   Split shift instructions to per-XLEN variants
> 
> Because shift instructions are so basic and XLEN-checking is so simple,
> I chose the former.  The latter is used on my Zfinx fixes but this is
> because register pair checking involves relatively complex per-operand
> constraints.  Complex solution for simple problem can be a new problem.
> 
> But...
> 
> -   Is it okay to add an argument anyway?
> -   Which is better extra argument?
>     1.  unsigned xlen
>     2.  const riscv_parse_subset_t * subset
>         which contains ISA version, XLEN and extensions
>         ... but a part of BFD, not opcodes.
> 
> I also (slightly) changed the assembler to suppress extra error message
> just like I did on Zicbop instructions:
> <https://sourceware.org/pipermail/binutils/2021-December/118910.html>
> <https://sourceware.org/pipermail/binutils/2021-December/118938.html>
> 
> 
> 
> 
> Tsukasa OI (3):
>   RISC-V: Add xlen to match_func
>   RISC-V: Check shift amount against XLEN
>   RISC-V: Add disassembler tests for shift amount
> 
>  gas/config/tc-riscv.c                  |   8 +-
>  gas/testsuite/gas/riscv/shamt-dis-32.d |  34 +++++++
>  gas/testsuite/gas/riscv/shamt-dis-64.d |  34 +++++++
>  gas/testsuite/gas/riscv/shamt-dis.s    |  45 +++++++++
>  include/opcode/riscv.h                 |   3 +-
>  opcodes/riscv-dis.c                    |   2 +-
>  opcodes/riscv-opc.c                    | 122 +++++++++++++++----------
>  sim/riscv/sim-main.c                   |   2 +-
>  8 files changed, 195 insertions(+), 55 deletions(-)
>  create mode 100644 gas/testsuite/gas/riscv/shamt-dis-32.d
>  create mode 100644 gas/testsuite/gas/riscv/shamt-dis-64.d
>  create mode 100644 gas/testsuite/gas/riscv/shamt-dis.s
> 
> 
> base-commit: cb0d58bf4d274cfb1ae11b75bd2b3ba81c8d371d