[PATCH v2 2/6] LoongArch:opcodes: Add new reloc types.

[liuzhensong]

在 2022/7/21 上午10:30, Xi Ruoyao 写道:
> On Thu, 2022-07-21 at 09:37 +0800, liuzhensong wrote:
>> +#define INSN_LA_ABS64                  \
>> +  "lu12i.w %1,%%abs_hi20(%2);"         \
>> +  "ori %1,%1,%%abs_lo12(%2);"          \
>> +  "lu32i.d %1,%%abs64_lo20(%2);"       \
>> +  "lu52i.d %1,%1,%%abs64_hi12(%2);",   \
>> +  &LARCH_opts.ase_lp64, 0
> Is it possible to use
>
> lu12i.w %1, %%abs_hi20(%2)
> lu32i.d %1, %%abs_lo12(%2)
> lu52i.d %1, %1, %%abs64_hi12(%2)
> addi.d  %1, %1, %%abs64_lo12(%2)
>
> so a future linker relaxation (or some optimization, anyway) may combine
> the last addi.d instruction with a following ld instruction?  Like
>
> la.abs64 $t0, foo
> ld.d     $t0, $t0, 0
>
> =>
>
> lu12i.w $t0, %abs_hi20(foo)
> lu32i.d $t0, %abs_lo12(foo)
> lu52i.d $t0, $t0, %abs64_hi12(foo)
> ld.d    $t0, $t0, %abs64_lo12(foo)
>
> (Doing so will need to take the highest bit of lo12 as a carry into the
> higher 52 bits.)
>
It seems default for addi.d/ld.d to access extreme address.

Simple example of abs32:

address range of abs32 : 0~0xffffffff

sym address: 0xfffff800

lui12.w $rd, 0xfffff

ori $rd, $d, 0x800

$rd is 0xfffff800

Obviously, lu12i.w and addi.w/ld.w can not get address > 0xfffff7fc abs64 is exactly same as abs32.
However, it is good idea to replace (lu12i.w,ori,ld.w) with (lu12i.w ld.w) if sym address in range -2G-2k  ~~  +2G-2k?