[PATCH 1/3] RISC-V: Add 'M' extension testcases

[Tsukasa OI]

On 2022/07/12 17:38, 廖仕华 wrote:
>> This commit adds basic 'M' (multiply/divide) extension testcases.
>>
>> gas/ChangeLog:
>>
>> 	* testsuite/gas/riscv/m-ext.s: New test.
>> 	* testsuite/gas/riscv/m-ext-32.d: New test (RV32).
>> 	* testsuite/gas/riscv/m-ext-64.d: New test (RV64).
>> 	* testsuite/gas/riscv/m-ext-fail-xlen-32.d: New test (failure
>> 	by using RV64-only instructions in RV32).
>> 	* testsuite/gas/riscv/m-ext-fail-xlen-32.l: Likewise.
>> ---
>>  gas/testsuite/gas/riscv/m-ext-32.d           | 18 +++++++++++++++
>>  gas/testsuite/gas/riscv/m-ext-64.d           | 23 ++++++++++++++++++++
>>  gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d |  4 ++++
>>  gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l |  6 +++++
>>  gas/testsuite/gas/riscv/m-ext.s              | 21 ++++++++++++++++++
>>  5 files changed, 72 insertions(+)
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-32.d
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-64.d
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
>>  create mode 100644 gas/testsuite/gas/riscv/m-ext.s
>>
>> diff --git a/gas/testsuite/gas/riscv/m-ext-32.d b/gas/testsuite/gas/riscv/m-ext-32.d
>> new file mode 100644
>> index 00000000000..fe2ef9af54b
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/m-ext-32.d
>> @@ -0,0 +1,18 @@
>> +#as: -march=rv32im
>> +#source: m-ext.s
>> +#objdump: -d
>> +
>> +.*:[ 	]+file format .*
>> +
>> +
>> +Disassembly of section .text:
>> +
>> +0+000 <target>:
>> +[ 	]+[0-9a-f]+:[ 	]+02c58533[ 	]+mul[  	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c59533[ 	]+mulh[ 	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5a533[ 	]+mulhsu[ 	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5b533[ 	]+mulhu[ 	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5c533[ 	]+div[  	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5d533[ 	]+divu[ 	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5e533[ 	]+rem[  	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5f533[ 	]+remu[ 	]+a0,a1,a2
>> diff --git a/gas/testsuite/gas/riscv/m-ext-64.d b/gas/testsuite/gas/riscv/m-ext-64.d
>> new file mode 100644
>> index 00000000000..6f1c3cd445b
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/m-ext-64.d
>> @@ -0,0 +1,23 @@
>> +#as: -march=rv64im -defsym __64_bit__=1
>> +#source: m-ext.s
>> +#objdump: -d
>> +
>> +.*:[ 	]+file format .*
>> +
>> +
>> +Disassembly of section .text:
>> +
>> +0+000 <target>:
>> +[ 	]+[0-9a-f]+:[ 	]+02c58533[ 	]+mul[  	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c59533[ 	]+mulh[ 	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5a533[ 	]+mulhsu[ 	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5b533[ 	]+mulhu[ 	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5c533[ 	]+div[  	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5d533[ 	]+divu[ 	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5e533[ 	]+rem[  	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5f533[ 	]+remu[ 	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5853b[ 	]+mulw[ 	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5c53b[ 	]+divw[ 	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5d53b[ 	]+divuw[ 	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5e53b[ 	]+remw[ 	]+a0,a1,a2
>> +[ 	]+[0-9a-f]+:[ 	]+02c5f53b[ 	]+remuw[ 	]+a0,a1,a2
>> diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
>> new file mode 100644
>> index 00000000000..cf254cbc476
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.d
>> @@ -0,0 +1,4 @@
>> +#as: -march=rv32im -defsym __64_bit__=1
>> +#source: m-ext.s
>> +#objdump: -d
>> +#error_output: m-ext-fail-xlen-32.l
>> diff --git a/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
>> new file mode 100644
>> index 00000000000..d65ca4980e6
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/m-ext-fail-xlen-32.l
>> @@ -0,0 +1,6 @@
>> +.*Assembler messages:
>> +.*: Error: unrecognized opcode `mulw a0,a1,a2'
>> +.*: Error: unrecognized opcode `divw a0,a1,a2'
>> +.*: Error: unrecognized opcode `divuw a0,a1,a2'
>> +.*: Error: unrecognized opcode `remw a0,a1,a2'
>> +.*: Error: unrecognized opcode `remuw a0,a1,a2'
>> diff --git a/gas/testsuite/gas/riscv/m-ext.s b/gas/testsuite/gas/riscv/m-ext.s
>> new file mode 100644
>> index 00000000000..c62317d5a62
>> --- /dev/null
>> +++ b/gas/testsuite/gas/riscv/m-ext.s
>> @@ -0,0 +1,21 @@
>> +target:
>> +	mul	a0, a1, a2
>> +	mulh	a0, a1, a2
>> +	mulhsu	a0, a1, a2
>> +	mulhu	a0, a1, a2
>> +.ifndef __zmmul__
> When gcc use -march=rv*_zmmul, "/*__riscv_zmmul */" will be generated.
> So, I think use "/*ifndf __riscv_zmmul */" is better

Thanks for the feedback but I feel that current names are good enough.

This is because they are intentionally differentiated from __riscv_zmmul
and __riscv_xlen because we want to switch the options manually (to
enable testing some mismatched configurations).  Even if they are not
defined in GAS, I didn't want to give wrong impressions.


>From PATCH 2/3:
diff --git a/gas/testsuite/gas/riscv/zmmul-32.d
b/gas/testsuite/gas/riscv/zmmul-32.d
new file mode 100644
index 00000000000..cf76e34ce1e
--- /dev/null
+++ b/gas/testsuite/gas/riscv/zmmul-32.d
@@ -0,0 +1,14 @@
+#as: -march=rv32im -defsym __zmmul__=1

>From PATCH 3/3 (mismatched configuration):
diff --git a/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
new file mode 100644
index 00000000000..af58c6f3d35
--- /dev/null
+++ b/gas/testsuite/gas/riscv/m-ext-fail-zmmul-64.d
@@ -0,0 +1,4 @@
+#as: -march=rv64i_zmmul -defsym __64_bit__=1


>> +	div	a0, a1, a2
>> +	divu	a0, a1, a2
>> +	rem	a0, a1, a2
>> +	remu	a0, a1, a2
>> +.endif
>> +
>> +.ifdef __64_bit__
> Similarly, use "/*__riscv_xlen == 64*/ " would better.

Well, actually, the __64_bit__ name came from
gas/testsuite/gas/riscv/ext.s.  I wasn't thinking much about the names
enough at the first time I wrote this testcases but now I'm confident
that this name is good enough.

But maybe not the best.  "zmmul" and "rv64" without leading underscores
(differentiated from ANY auto-generated macros) may be an option.

Thanks,
Tsukasa

>> +	mulw	a0, a1, a2
>> +.ifndef __zmmul__
>> +	divw	a0, a1, a2
>> +	divuw	a0, a1, a2
>> +	remw	a0, a1, a2
>> +	remuw	a0, a1, a2
>> +.endif
>> +.endif
>> -- 
>> 2.34.1
>