[PATCH 0/2] RISC-V: Improve "bits undefined" diagnostics

[Tsukasa OI]

Hello,

This small patch intends to improve one of the internal diagnostic messages
when an invalid RISC-V instruction is defined in riscv-opc.c.

Tracker on GitHub:
<https://github.com/a4lg/binutils-gdb/wiki/riscv_gas_diag_unused_bits>

    Sidenote:
    I started listing my Binutils submissions on my GitHub Wiki:
    <https://github.com/a4lg/binutils-gdb/wiki/Patch-Queue>
    hoping that current status and conflicting patches are clear.

So, priority to apply this patch is VERY LOW
(definitely, this is the last patchset sent by me to be reviewed).

However, I believe that applying this patch improves experient while testing
new RISC-V instructions (or modifying RISC-V instructions in somy way).



First -- just to experiment -- we change mask value of "fcvt.d.s"
instruction from MASK_FCVT_D_S|MASK_RM to MASK_FCVT_D_S while not touching
operands "D,S" and we run compiled assembler, we get following message:

    Assembler messages:
    Error: internal: bad RISC-V opcode (bits 0xffffffff00007000 undefined): fcvt.d.s D,S
    Fatal error: internal: broken assembler.  No assembly attempted

Bits 0x7000 corresponds to rm (rounding mode) bits we just removed and no
corresponding operands are found (making definition of fcvt.d.s instruction
invalid).

Then, what about 0xffffffff00000000 (upper 32-bits)?
Yes, they are non-instruction bits.  Because of ~ (bitwise complement)
operator while computing undefined bits, it also displays non-instruction
bits.


This patchset (PATCH 1/2) changes how undefined/invalid bits are computed.

before:
    ~(used & required)
after:
    (used ^ required)

After PATCH 1/2, following error message is generated.

    Assembler messages:
    Error: internal: bad RISC-V opcode (bits 0x7000 undefined or invalid): fcvt.d.s D,S
    Fatal error: internal: broken assembler.  No assembly attempted


Note that we are testing for "undefined or invalid" bits here, not just
undefined bits.  In fact, if we corrupt a variant of c.addi instruction with
ADDITIONAL "j" operand (which is an immediate for I-type instruction, upper
12-bits of **32-bit** instruction encoding), we get following message:

    Assembler messages:
    Error: internal: bad RISC-V opcode (bits 0xfff00000 undefined or invalid): addi d,CU,Cj,j
    Fatal error: internal: broken assembler.  No assembly attempted

Okay, extra "j" operand generates "extra" bits (that should not have been
defined considering its 16-bit encoding) and words "undefined or invalid"
are working here.  We are correctly capturing invalid extra bits.  Before
this patch, invalid bits are hidden by 0xffffffffffff0000 (48 non-
instruction bits).


Additionally, this patchset includes a minor fix when unsigned long long
type is larger than 64-bits.  It also works to correct computing required
bits (PATCH 2/2).


Again, this patch is not important but anyway, happy hacking!

Thanks,
Tsukasa




Tsukasa OI (2):
  RISC-V: Improve "bits undefined" diagnostics
  RISC-V: Fix required bits on certain environments

 gas/config/tc-riscv.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)


base-commit: d2acd4b0c5bab349aaa152d60268bc144634a844
-- 
2.34.1