[PATCH 0/4] x86: opcode table tidying

[Jan Beulich]

On 06.01.2022 16:10, H.J. Lu wrote:
> On Thu, Jan 6, 2022 at 6:56 AM Jan Beulich <jbeulich@suse.com> wrote:
>>
>> On 06.01.2022 15:31, H.J. Lu wrote:
>>> On Thu, Jan 6, 2022 at 5:52 AM Jan Beulich <jbeulich@suse.com> wrote:
>>>>
>>>> On 06.01.2022 14:47, H.J. Lu wrote:
>>>>> On Thu, Jan 6, 2022 at 5:24 AM Jan Beulich <jbeulich@suse.com> wrote:
>>>>>>
>>>>>> On 05.01.2022 15:58, H.J. Lu wrote:
>>>>>>> On Wed, Jan 05, 2022 at 12:20:05PM +0100, Jan Beulich wrote:
>>>>>>>> 1: templatize FMA insn templates
>>>>>>>> 2: drop some "comm" template parameters
>>>>>>>> 3: drop NoAVX from POPCNT
>>>>>>>> 4: drop NoAVX insn attribute
>>>>>>>>
>>>>>>>
>>>>>>> OK for all.
>>>>>>
>>>>>> Thanks. I've committed the series, but I wonder whether you have an
>>>>>> opinion on the SSE4a aspect mentioned in the last patch.
>>>>>
>>>>> Do you have a patch?
>>>>
>>>> A patch to do what, exactly? (IOW: In order to perhaps make a patch, I
>>>> need to understand what the intentions are.)
>>>
>>> Please open a bug report to describe the issue.
>>
>> I guess I'll give up here. I can't know whether there's a bug without
>> knowing what the intentions are. Documentation also isn't sufficiently
>> clear / unambiguous. And I'm not willing to abuse bugzilla for having
>> a discussion; that's what I thought the mailing list is for.
> 
> Are there any SSE instructions in SSE4a that aren't checked?

Well, all of them are excluded from checking. There's even a test
for one of them checking that no diagnostic would be issued.

> If yes, is it a bug?

That's the question. What is unclear to me in particular is
- whether a diagnostic is to be issued only for insns which have
  AVX equivalents (and hence can easily be replaced),
- whether the issue that we try to point out by the diagnostic
  actually is applicable to any AMD CPU.

Jan