[PATCH 3/3] RISC-V: Add testcases and disassemble support for z[fdq]inx
Nelson Chu
nelson.chu@sifive.com
Tue Nov 9 10:03:37 GMT 2021
Umm, adding a new flag in the elf header needs to change the riscv
psabi, but in fact we could try to get the information from the elf
architecture attribute. I have sent a patch to let dis-assembler can
access the elf attributes, and then parse the architecture string:
https://sourceware.org/pipermail/binutils/2021-November/118444.html
So that you can call "riscv_subset_supports (&riscv_rps_dis, "zfinx")"
to check if the zfinx extension is enable or not, and without adding
and checking the new elf header flag.
I will commit my patch in a few days, so please feel free to contact
me if you have any questions.
Thanks
Nelson
On Fri, Oct 29, 2021 at 12:50 AM jiawei <jiawei@iscas.ac.cn> wrote:
>
> ---
> binutils/readelf.c | 3 +++
> gas/config/tc-riscv.c | 15 ++++++++++++
> gas/testsuite/gas/riscv/zdinx.d | 41 +++++++++++++++++++++++++++++++
> gas/testsuite/gas/riscv/zdinx.s | 33 +++++++++++++++++++++++++
> gas/testsuite/gas/riscv/zfinx.d | 39 ++++++++++++++++++++++++++++++
> gas/testsuite/gas/riscv/zfinx.s | 31 ++++++++++++++++++++++++
> gas/testsuite/gas/riscv/zqinx.d | 43 +++++++++++++++++++++++++++++++++
> gas/testsuite/gas/riscv/zqinx.s | 35 +++++++++++++++++++++++++++
> include/elf/riscv.h | 3 +++
> opcodes/riscv-dis.c | 4 +++
> 10 files changed, 247 insertions(+)
> create mode 100644 gas/testsuite/gas/riscv/zdinx.d
> create mode 100644 gas/testsuite/gas/riscv/zdinx.s
> create mode 100644 gas/testsuite/gas/riscv/zfinx.d
> create mode 100644 gas/testsuite/gas/riscv/zfinx.s
> create mode 100644 gas/testsuite/gas/riscv/zqinx.d
> create mode 100644 gas/testsuite/gas/riscv/zqinx.s
>
> diff --git a/binutils/readelf.c b/binutils/readelf.c
> index 682eacdef14..fc889c6c3ff 100644
> --- a/binutils/readelf.c
> +++ b/binutils/readelf.c
> @@ -3717,6 +3717,9 @@ get_machine_flags (Filedata * filedata, unsigned e_flags, unsigned e_machine)
> if (e_flags & EF_RISCV_RVE)
> strcat (buf, ", RVE");
>
> + if (e_flags & EF_RISCV_ZFINX)
> + strcat (buf, ", ZFINX");
> +
> switch (e_flags & EF_RISCV_FLOAT_ABI)
> {
> case EF_RISCV_FLOAT_ABI_SOFT:
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index b879bf1ea8b..ff279263ffb 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -204,6 +204,7 @@ struct riscv_set_options
> int pic; /* Generate position-independent code. */
> int rvc; /* Generate RVC code. */
> int rve; /* Generate RVE code. */
> + int zfinx; /* Generate ZFINX code. */
> int relax; /* Emit relocs the linker is allowed to relax. */
> int arch_attr; /* Emit architecture and privileged elf attributes. */
> int csr_check; /* Enable the CSR checking. */
> @@ -214,6 +215,7 @@ static struct riscv_set_options riscv_opts =
> 0, /* pic */
> 0, /* rvc */
> 0, /* rve */
> + 0, /* ZFINX */
> 1, /* relax */
> DEFAULT_RISCV_ATTR, /* arch_attr */
> 0, /* csr_check */
> @@ -234,6 +236,15 @@ riscv_set_rve (bool rve_value)
> riscv_opts.rve = rve_value;
> }
>
> +static void
> +riscv_set_zfinx (bool finx_value)
> +{
> + if (finx_value)
> + elf_flags |= EF_RISCV_ZFINX;
> +
> + riscv_opts.finx = finx_value;
> +}
> +
> static riscv_subset_list_t riscv_subsets;
>
> static bool
> @@ -328,6 +339,10 @@ riscv_set_arch (const char *s)
> riscv_set_rve (false);
> if (riscv_subset_supports ("e"))
> riscv_set_rve (true);
> + if (riscv_subset_supports ("zfinx")
> + || riscv_subset_supports ("zdinx")
> + || riscv_subset_supports ("zqinx"))
> + riscv_set_finx (true);
> }
>
> /* Indicate -mabi option is explictly set. */
> diff --git a/gas/testsuite/gas/riscv/zdinx.d b/gas/testsuite/gas/riscv/zdinx.d
> new file mode 100644
> index 00000000000..3e4c1a73388
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zdinx.d
> @@ -0,0 +1,41 @@
> +#as: -march=rv64ima_zdinx
> +#source: zdinx.s
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.d[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.d[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.d[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.d[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.d[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.d[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.d[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.d[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.d[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.d[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.d.s[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.d.w[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.d.wu[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.d.l[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.d.lu[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2c5a553[ ]+feq.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2c59553[ ]+flt.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.d[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.d[ ]+a0,a2,a1
> +[ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.d[ ]+a0,a2,a1
> +[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.d[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.d[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.d[ ]+a0,a1
> diff --git a/gas/testsuite/gas/riscv/zdinx.s b/gas/testsuite/gas/riscv/zdinx.s
> new file mode 100644
> index 00000000000..c427d982aaf
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zdinx.s
> @@ -0,0 +1,33 @@
> +target:
> + fadd.d a0, a1, a2
> + fsub.d a0, a1, a2
> + fmul.d a0, a1, a2
> + fdiv.d a0, a1, a2
> + fsqrt.d a0, a0
> + fmin.d a0, a1, a2
> + fmax.d a0, a1, a2
> + fmadd.d a0, a1, a2, a3
> + fnmadd.d a0, a1, a2, a3
> + fmsub.d a0, a1, a2, a3
> + fnmsub.d a0, a1, a2, a3
> + fcvt.w.d a0, a1
> + fcvt.wu.d a0, a1
> + fcvt.l.d a0, a1
> + fcvt.lu.d a0, a1
> + fcvt.s.d a0, a1
> + fcvt.d.s a0, a1
> + fcvt.d.w a0, a1
> + fcvt.d.wu a0, a1
> + fcvt.d.l a0, a1
> + fcvt.d.lu a0, a1
> + fsgnj.d a0, a1, a2
> + fsgnjn.d a0, a1, a2
> + fsgnjx.d a0, a1, a2
> + feq.d a0, a1, a2
> + flt.d a0, a1, a2
> + fle.d a0, a1, a2
> + fgt.d a0, a1, a2
> + fge.d a0, a1, a2
> + fneg.d a0, a0
> + fabs.d a0, a0
> + fclass.d a0, a1
> diff --git a/gas/testsuite/gas/riscv/zfinx.d b/gas/testsuite/gas/riscv/zfinx.d
> new file mode 100644
> index 00000000000..d5499aa9131
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfinx.d
> @@ -0,0 +1,39 @@
> +#as: -march=rv64ima_zfinx
> +#source: zfinx.s
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+08c5f553[ ]+fsub.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+10c5f553[ ]+fmul.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+18c5f553[ ]+fdiv.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+58057553[ ]+fsqrt.s[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+28c58553[ ]+fmin.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+28c59553[ ]+fmax.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+68c5f543[ ]+fmadd.s[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+68c5f54f[ ]+fnmadd.s[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+68c5f547[ ]+fmsub.s[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+68c5f54b[ ]+fnmsub.s[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+c005f553[ ]+fcvt.w.s[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c015f553[ ]+fcvt.wu.s[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c025f553[ ]+fcvt.l.s[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c035f553[ ]+fcvt.lu.s[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d005f553[ ]+fcvt.s.w[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d015f553[ ]+fcvt.s.wu[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d025f553[ ]+fcvt.s.l[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d035f553[ ]+fcvt.s.lu[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+20c58553[ ]+fsgnj.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c59553[ ]+fsgnjn.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+20c5a553[ ]+fsgnjx.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a0c5a553[ ]+feq.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a0c59553[ ]+flt.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a0c58553[ ]+fle.s[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a0b61553[ ]+flt.s[ ]+a0,a2,a1
> +[ ]+[0-9a-f]+:[ ]+a0b60553[ ]+fle.s[ ]+a0,a2,a1
> +[ ]+[0-9a-f]+:[ ]+20a51553[ ]+fneg.s[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+20a52553[ ]+fabs.s[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+e0059553[ ]+fclass.s[ ]+a0,a1
> diff --git a/gas/testsuite/gas/riscv/zfinx.s b/gas/testsuite/gas/riscv/zfinx.s
> new file mode 100644
> index 00000000000..af50490fadf
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zfinx.s
> @@ -0,0 +1,31 @@
> +target:
> + fadd.s a0, a1, a2
> + fsub.s a0, a1, a2
> + fmul.s a0, a1, a2
> + fdiv.s a0, a1, a2
> + fsqrt.s a0, a0
> + fmin.s a0, a1, a2
> + fmax.s a0, a1, a2
> + fmadd.s a0, a1, a2, a3
> + fnmadd.s a0, a1, a2, a3
> + fmsub.s a0, a1, a2, a3
> + fnmsub.s a0, a1, a2, a3
> + fcvt.w.s a0, a1
> + fcvt.wu.s a0, a1
> + fcvt.l.s a0, a1
> + fcvt.lu.s a0, a1
> + fcvt.s.w a0, a1
> + fcvt.s.wu a0, a1
> + fcvt.s.l a0, a1
> + fcvt.s.lu a0, a1
> + fsgnj.s a0, a1, a2
> + fsgnjn.s a0, a1, a2
> + fsgnjx.s a0, a1, a2
> + feq.s a0, a1, a2
> + flt.s a0, a1, a2
> + fle.s a0, a1, a2
> + fgt.s a0, a1, a2
> + fge.s a0, a1, a2
> + fneg.s a0, a0
> + fabs.s a0, a0
> + fclass.s a0, a1
> diff --git a/gas/testsuite/gas/riscv/zqinx.d b/gas/testsuite/gas/riscv/zqinx.d
> new file mode 100644
> index 00000000000..a1c9eab4e1d
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zqinx.d
> @@ -0,0 +1,43 @@
> +#as: -march=rv64ima_zqinx
> +#source: zqinx.s
> +#objdump: -dr
> +
> +.*:[ ]+file format .*
> +
> +Disassembly of section .text:
> +
> +0+000 <target>:
> +[ ]+[0-9a-f]+:[ ]+02c5f553[ ]+fadd.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+0ac5f553[ ]+fsub.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+12c5f553[ ]+fmul.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+1ac5f553[ ]+fdiv.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+5a057553[ ]+fsqrt.q[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+2ac58553[ ]+fmin.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+2ac59553[ ]+fmax.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+6ac5f543[ ]+fmadd.q[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+6ac5f54f[ ]+fnmadd.q[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+6ac5f547[ ]+fmsub.q[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+6ac5f54b[ ]+fnmsub.q[ ]+a0,a1,a2,a3
> +[ ]+[0-9a-f]+:[ ]+c205f553[ ]+fcvt.w.q[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c215f553[ ]+fcvt.wu.q[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c225f553[ ]+fcvt.l.q[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+c235f553[ ]+fcvt.lu.q[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.s.q[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+4015f553[ ]+fcvt.d.q[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+46058553[ ]+fcvt.q.s[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+42058553[ ]+fcvt.q.d[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d2058553[ ]+fcvt.q.w[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d2158553[ ]+fcvt.q.wu[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d225f553[ ]+fcvt.q.l[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+d235f553[ ]+fcvt.q.lu[ ]+a0,a1
> +[ ]+[0-9a-f]+:[ ]+22c58553[ ]+fsgnj.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+22c59553[ ]+fsgnjn.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+22c5a553[ ]+fsgnjx.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2c5a553[ ]+feq.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2c59553[ ]+flt.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2c58553[ ]+fle.q[ ]+a0,a1,a2
> +[ ]+[0-9a-f]+:[ ]+a2b61553[ ]+flt.q[ ]+a0,a2,a1
> +[ ]+[0-9a-f]+:[ ]+a2b60553[ ]+fle.q[ ]+a0,a2,a1
> +[ ]+[0-9a-f]+:[ ]+22a51553[ ]+fneg.q[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+22a52553[ ]+fabs.q[ ]+a0,a0
> +[ ]+[0-9a-f]+:[ ]+e2059553[ ]+fclass.q[ ]+a0,a1
> diff --git a/gas/testsuite/gas/riscv/zqinx.s b/gas/testsuite/gas/riscv/zqinx.s
> new file mode 100644
> index 00000000000..8372ba57c71
> --- /dev/null
> +++ b/gas/testsuite/gas/riscv/zqinx.s
> @@ -0,0 +1,35 @@
> +target:
> + fadd.q a0, a1, a2
> + fsub.q a0, a1, a2
> + fmul.q a0, a1, a2
> + fdiv.q a0, a1, a2
> + fsqrt.q a0, a0
> + fmin.q a0, a1, a2
> + fmax.q a0, a1, a2
> + fmadd.q a0, a1, a2, a3
> + fnmadd.q a0, a1, a2, a3
> + fmsub.q a0, a1, a2, a3
> + fnmsub.q a0, a1, a2, a3
> + fcvt.w.q a0, a1
> + fcvt.wu.q a0, a1
> + fcvt.l.q a0, a1
> + fcvt.lu.q a0, a1
> + fcvt.s.q a0, a1
> + fcvt.d.q a0, a1
> + fcvt.q.s a0, a1
> + fcvt.q.d a0, a1
> + fcvt.q.w a0, a1
> + fcvt.q.wu a0, a1
> + fcvt.q.l a0, a1
> + fcvt.q.lu a0, a1
> + fsgnj.q a0, a1, a2
> + fsgnjn.q a0, a1, a2
> + fsgnjx.q a0, a1, a2
> + feq.q a0, a1, a2
> + flt.q a0, a1, a2
> + fle.q a0, a1, a2
> + fgt.q a0, a1, a2
> + fge.q a0, a1, a2
> + fneg.q a0, a0
> + fabs.q a0, a0
> + fclass.q a0, a1
> diff --git a/include/elf/riscv.h b/include/elf/riscv.h
> index 80822835cd9..a73623d315d 100644
> --- a/include/elf/riscv.h
> +++ b/include/elf/riscv.h
> @@ -114,6 +114,9 @@ END_RELOC_NUMBERS (R_RISCV_max)
> /* File uses the 32E base integer instruction. */
> #define EF_RISCV_RVE 0x0008
>
> +/* File uses the gpr base ZFINX instruction. */
> +#define EF_RISCV_ZFINX 0x0010
> +
> /* The name of the global pointer symbol. */
> #define RISCV_GP_SYMBOL "__global_pointer$"
>
> diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
> index 2e28ba77e60..4bf640e6f53 100644
> --- a/opcodes/riscv-dis.c
> +++ b/opcodes/riscv-dis.c
> @@ -513,6 +513,10 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info)
> xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32;
> }
>
> + /* If ELF has ZFINX flags, use gpr for disassemble. */
> + if ((ehdr->e_flags & EF_RISCV_ZFINX_ABI) == EF_RISCV_ZFINX_ABI)
> + riscv_fpr_names = riscv_gpr_names_abi;
> +
> for (; op->name; op++)
> {
> /* Does the opcode match? */
> --
> 2.25.1
>
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