[PATCH v2 1/6] RISC-V: Support assembly and disassembly in big endian mode

[Nelson Chu]

On Sun, Dec 20, 2020 at 7:30 PM Marcus Comstedt <marcus@mc.pp.se> wrote:
>
> bfd/
>         * config.bfd: Add riscv_elf32_be_vec and riscv_elf64_be_vec.
>         * configure.ac: Likewise.
>         * configure: Regenerate.
>         * elfnn-riscv.c: (riscv_elf_object_p): Recognize elf32-bigriscv
>         as 32-bit mach.
>         (TARGET_BIG_SYM, TARGET_BIG_NAME): Add them.
>         * targets.c: Add riscv_elf32_be_vec and riscv_elf64_be_vec.
>
> gas/
>         * config/tc-riscv.c (riscv_target_format): Add elf64-bigriscv
>         and elf32-bigriscv.
>         (install_insn): Always write instructions as little endian.
>         (md_number_to_chars): Write data in target endianness.
>         (options): Add OPTION_BIG_ENDIAN and OPTION_LITTLE_ENDIAN.
>         (md_longopts): Likewise.
>         (md_parse_option): Likewise.

I can not build the default big-endian binutils by setting
--target=riscv32be-unknow-elf.  You can refer to what other targets
did in the gas/configure.tgt, to set the `endian` correctly;
Otherwise, lots of ld testcases are broken and failed.  And you also
need to update the gas/config/tc-riscv.h file, to only set the
TARGET_BYTES_BIG_ENDIAN if it is undefined.

Thanks
Nelson