Add support for Intel SERIALIZE instructions
Cui, Lili
lili.cui@intel.com
Thu Apr 2 04:01:08 GMT 2020
Hi all,
This patch is about to enable binutils support for SERIALIZE which would be in GLC.
There's only 1 instruction: SERIALIZE,
more details please refer to https://software.intel.com/sites/default/files/managed/c5/15/architecture-instruction-set-extensions-programming-reference.pdf
Make check-gas is ok.
gas/ChangeLog:
2020-04-02 Lili Cui <lili.cui@intel.com>
* config/tc-i386.c (cpu_arch): Add .serialize.
(cpu_noarch): Likewise.
* doc/c-i386.texi: Document serialize.
* testsuite/gas/i386/i386.exp: Run serialize tests
* testsuite/gas/i386/serialize.d: Likewise.
* testsuite/gas/i386/x86-64-serialize.d: Likewise.
* testsuite/gas/i386/serialize.s: Likewise.
opcodes/ChangeLog:
2020-04-02 Lili Cui <lili.cui@intel.com>
* i386-dis.c (prefix_table): New instructions serialize.
* i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
CPU_ANY_SERIALIZE_FLAGS.
(cpu_flags): Add CpuSERIALIZE.
* i386-opc.h (enum): Add CpuSERIALIZE.
(i386_cpu_flags): Add cpuserialize.
* i386-opc.tbl: Add SERIALIZE insns.
* i386-init.h: Regenerate.
* i386-tbl.h: Likewise.
---
gas/config/tc-i386.c | 3 +++
gas/doc/c-i386.texi | 2 ++
gas/testsuite/gas/i386/i386.exp | 2 ++
gas/testsuite/gas/i386/serialize.d | 13 +++++++++++++
gas/testsuite/gas/i386/serialize.s | 6 ++++++
gas/testsuite/gas/i386/x86-64-serialize.d | 13 +++++++++++++
opcodes/i386-dis.c | 2 +-
opcodes/i386-gen.c | 5 +++++
opcodes/i386-opc.h | 3 +++
opcodes/i386-opc.tbl | 6 ++++++
10 files changed, 54 insertions(+), 1 deletion(-)
create mode 100644 gas/testsuite/gas/i386/serialize.d
create mode 100644 gas/testsuite/gas/i386/serialize.s
create mode 100644 gas/testsuite/gas/i386/x86-64-serialize.d
diff --git a/gas/config/tc-i386.c b/gas/config/tc-i386.c
index 09063f784b..d67532c422 100644
--- a/gas/config/tc-i386.c
+++ b/gas/config/tc-i386.c
@@ -1206,6 +1206,8 @@ static const arch_entry cpu_arch[] =
CPU_AVX512_VP2INTERSECT_FLAGS, 0 },
{ STRING_COMMA_LEN (".enqcmd"), PROCESSOR_UNKNOWN,
CPU_ENQCMD_FLAGS, 0 },
+ { STRING_COMMA_LEN (".serialize"), PROCESSOR_UNKNOWN,
+ CPU_SERIALIZE_FLAGS, 0 },
{ STRING_COMMA_LEN (".rdpru"), PROCESSOR_UNKNOWN,
CPU_RDPRU_FLAGS, 0 },
{ STRING_COMMA_LEN (".mcommit"), PROCESSOR_UNKNOWN,
@@ -1255,6 +1257,7 @@ static const noarch_entry cpu_noarch[] =
{ STRING_COMMA_LEN ("noavx512_bf16"), CPU_ANY_AVX512_BF16_FLAGS },
{ STRING_COMMA_LEN ("noavx512_vp2intersect"), CPU_ANY_SHSTK_FLAGS },
{ STRING_COMMA_LEN ("noenqcmd"), CPU_ANY_ENQCMD_FLAGS },
+ { STRING_COMMA_LEN ("noserialize"), CPU_ANY_SERIALIZE_FLAGS },
};
#ifdef I386COFF
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 1dd99f91bb..d42148ed43 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -187,6 +187,7 @@ accept various extension mnemonics. For example,
@code{movdiri},
@code{movdir64b},
@code{enqcmd},
+@code{serialize},
@code{avx512f},
@code{avx512cd},
@code{avx512er},
@@ -221,6 +222,7 @@ accept various extension mnemonics. For example,
@code{noavx512_vp2intersect},
@code{noavx512_bf16},
@code{noenqcmd},
+@code{noserialize},
@code{vmx},
@code{vmfunc},
@code{smx},
diff --git a/gas/testsuite/gas/i386/i386.exp b/gas/testsuite/gas/i386/i386.exp
index f21131ed99..7961bb1f37 100644
--- a/gas/testsuite/gas/i386/i386.exp
+++ b/gas/testsuite/gas/i386/i386.exp
@@ -476,6 +476,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_32_check]]
run_dump_test "enqcmd"
run_dump_test "enqcmd-intel"
run_list_test "enqcmd-inval"
+ run_dump_test "serialize"
run_dump_test "vp2intersect"
run_dump_test "vp2intersect-intel"
run_list_test "vp2intersect-inval-bcast"
@@ -1052,6 +1053,7 @@ if [expr ([istarget "i*86-*-*"] || [istarget "x86_64-*-*"]) && [gas_64_check]] t
run_dump_test "x86-64-enqcmd"
run_dump_test "x86-64-enqcmd-intel"
run_list_test "x86-64-enqcmd-inval"
+ run_dump_test "x86-64-serialize"
run_dump_test "x86-64-vp2intersect"
run_dump_test "x86-64-vp2intersect-intel"
run_list_test "x86-64-vp2intersect-inval-bcast"
diff --git a/gas/testsuite/gas/i386/serialize.d b/gas/testsuite/gas/i386/serialize.d
new file mode 100644
index 0000000000..b947fb0550
--- /dev/null
+++ b/gas/testsuite/gas/i386/serialize.d
@@ -0,0 +1,13 @@
+#as:
+#objdump: -dw
+#name: SERIALIZE insns
+#source: serialize.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f 01 e8 + serialize *
+#pass
+
diff --git a/gas/testsuite/gas/i386/serialize.s b/gas/testsuite/gas/i386/serialize.s
new file mode 100644
index 0000000000..22444f5b1a
--- /dev/null
+++ b/gas/testsuite/gas/i386/serialize.s
@@ -0,0 +1,6 @@
+# Check SERIALIZE instructions.
+
+ .text
+_start:
+ serialize
+
diff --git a/gas/testsuite/gas/i386/x86-64-serialize.d b/gas/testsuite/gas/i386/x86-64-serialize.d
new file mode 100644
index 0000000000..66c51efae4
--- /dev/null
+++ b/gas/testsuite/gas/i386/x86-64-serialize.d
@@ -0,0 +1,13 @@
+#as:
+#objdump: -dw
+#name: x86_64 SERIALIZE insns
+#source: serialize.s
+
+.*: +file format .*
+
+Disassembly of section \.text:
+
+0+ <_start>:
+[ ]*[a-f0-9]+: 0f 01 e8 + serialize *
+#pass
+
diff --git a/opcodes/i386-dis.c b/opcodes/i386-dis.c
index 4a59619da4..89ab43c1ab 100644
--- a/opcodes/i386-dis.c
+++ b/opcodes/i386-dis.c
@@ -3644,7 +3644,7 @@ static const struct dis386 prefix_table[][4] = {
/* PREFIX_0F01_REG_5_MOD_3_RM_0 */
{
- { Bad_Opcode },
+ { "serialize", { Skip_MODRM }, PREFIX_OPCODE },
{ "setssbsy", { Skip_MODRM }, PREFIX_OPCODE },
},
diff --git a/opcodes/i386-gen.c b/opcodes/i386-gen.c
index 50dd2b6f19..3a6a4a0492 100644
--- a/opcodes/i386-gen.c
+++ b/opcodes/i386-gen.c
@@ -303,6 +303,8 @@ static initializer cpu_flag_init[] =
"CpuMOVDIR64B" },
{ "CPU_ENQCMD_FLAGS",
"CpuENQCMD" },
+ { "CPU_SERIALIZE_FLAGS",
+ "CpuSERIALIZE" },
{ "CPU_AVX512_VP2INTERSECT_FLAGS",
"CpuAVX512_VP2INTERSECT" },
{ "CPU_RDPRU_FLAGS",
@@ -385,6 +387,8 @@ static initializer cpu_flag_init[] =
"CpuMOVDIR64B" },
{ "CPU_ANY_ENQCMD_FLAGS",
"CpuENQCMD" },
+ { "CPU_ANY_SERIALIZE_FLAGS",
+ "CpuSERIALIZE" },
{ "CPU_ANY_AVX512_VP2INTERSECT_FLAGS",
"CpuAVX512_VP2INTERSECT" },
};
@@ -606,6 +610,7 @@ static bitfield cpu_flags[] =
BITFIELD (CpuMOVDIRI),
BITFIELD (CpuMOVDIR64B),
BITFIELD (CpuENQCMD),
+ BITFIELD (CpuSERIALIZE),
BITFIELD (CpuRDPRU),
BITFIELD (CpuMCOMMIT),
BITFIELD (CpuSEV_ES),
diff --git a/opcodes/i386-opc.h b/opcodes/i386-opc.h
index 480c979d19..f4f48871be 100644
--- a/opcodes/i386-opc.h
+++ b/opcodes/i386-opc.h
@@ -243,6 +243,8 @@ enum
CpuMOVDIR64B,
/* ENQCMD instruction required */
CpuENQCMD,
+ /* SERIALIZE instruction required */
+ CpuSERIALIZE,
/* RDPRU instruction required */
CpuRDPRU,
/* MCOMMIT instruction required */
@@ -378,6 +380,7 @@ typedef union i386_cpu_flags
unsigned int cpumovdiri:1;
unsigned int cpumovdir64b:1;
unsigned int cpuenqcmd:1;
+ unsigned int cpuserialize:1;
unsigned int cpurdpru:1;
unsigned int cpumcommit:1;
unsigned int cpusev_es:1;
diff --git a/opcodes/i386-opc.tbl b/opcodes/i386-opc.tbl
index 206447dc63..d697771724 100644
--- a/opcodes/i386-opc.tbl
+++ b/opcodes/i386-opc.tbl
@@ -4076,3 +4076,9 @@ mcommit, 0, 0xf30f01fa, None, 3, CpuMCOMMIT, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_
rdpru, 0, 0x0f01fd, None, 3, CpuRDPRU, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
// RDPRU instruction end
+
+//SERIALIZE instruction
+
+serialize, 0, 0x0f01e8, None, 3, CpuSERIALIZE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { 0 }
+
+//SERIALIZE instruction end
--
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