[PATCH][AArch64] Restrict MOV alias for ORR instruction

[Egeyar Bagcioglu]

Hello,

ARM Architecture Reference Manual for the profile ARMv8-A, Issue C.a, 
states that MOV (register) is an alias of the ORR (shifted register) iff 
shift == '00' && imm6 == '000000' && Rn == '11111'. However, mov is 
currently preferred for a broader range of orr instructions.

PR 23193 is filed for this purpose and still open. Another related one, 
19721 was filed earlier and resolved inconsistently with the manual.

The attached patch fixes the opcodes to match the manual in this regard, 
corrects existing test cases and adds new ones. I have re-used the test 
source and the driver of the older pr, 19721.

I did *not* replace the existing Rm_SFT used in the "mov" entry with an 
Rm. Therefore, "mov" usages with shifted registers such as "mov x7, x17, 
lsl 25" could continue to be accepted. However, they are not generated 
anymore.


The suggested change log is the following:

2018-10-30Â  Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>

 Â Â Â  [AArch64] Use MOV (register) as an alias for ORR (shifted register)
 Â Â Â  iff shift == '00' && imm6 == '000000' && Rn == '11111'.

 Â Â Â  gas/ChangeLog:
 Â Â Â Â Â Â Â  PR 23193
 Â Â Â Â Â Â Â  PR 19721
 Â Â Â Â Â Â Â  * testsuite/gas/aarch64/pr19721.s: Add new test cases.
 Â Â Â Â Â Â Â  * testsuite/gas/aarch64/pr19721.d: Correct existing test
 Â Â Â Â Â Â Â  cases and add new ones.

 Â Â Â  opcodes/ChangeLog:
 Â Â Â Â Â Â Â  PR 23193
 Â Â Â Â Â Â Â  PR 19721
 Â Â Â Â Â Â Â  * aarch64-tbl.h: Use MOV (register) as an alias for ORR (shifted
 Â Â Â Â Â Â Â  register) iff shift == '00' && imm6 == '000000' && Rn == '11111'.


Tested on aarch64-unknown-linux-gnu and showed no regressions.

Please take a look and apply if legitimate.

Regards,
Egeyar
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