[PATCH][AArch64] Restrict MOV alias for ORR instruction

[Richard Earnshaw (lists)]

On 30/10/2018 18:12, Egeyar Bagcioglu wrote:
> Hello,
> 
> ARM Architecture Reference Manual for the profile ARMv8-A, Issue C.a,
> states that MOV (register) is an alias of the ORR (shifted register) iff
> shift == '00' && imm6 == '000000' && Rn == '11111'. However, mov is
> currently preferred for a broader range of orr instructions.
> 
> PR 23193 is filed for this purpose and still open. Another related one,
> 19721 was filed earlier and resolved inconsistently with the manual.
> 
> The attached patch fixes the opcodes to match the manual in this regard,
> corrects existing test cases and adds new ones. I have re-used the test
> source and the driver of the older pr, 19721.
> 
> I did *not* replace the existing Rm_SFT used in the "mov" entry with an
> Rm. Therefore, "mov" usages with shifted registers such as "mov x7, x17,
> lsl 25" could continue to be accepted. However, they are not generated
> anymore.
> 
> 
> The suggested change log is the following:
> 
> 2018-10-30Â  Egeyar Bagcioglu <egeyar.bagcioglu@oracle.com>
> 
> Â Â Â  [AArch64] Use MOV (register) as an alias for ORR (shifted register)
> Â Â Â  iff shift == '00' && imm6 == '000000' && Rn == '11111'.
> 
> Â Â Â  gas/ChangeLog:
> Â Â Â Â Â Â Â  PR 23193
> Â Â Â Â Â Â Â  PR 19721
> Â Â Â Â Â Â Â  * testsuite/gas/aarch64/pr19721.s: Add new test cases.
> Â Â Â Â Â Â Â  * testsuite/gas/aarch64/pr19721.d: Correct existing test
> Â Â Â Â Â Â Â  cases and add new ones.
> 
> Â Â Â  opcodes/ChangeLog:
> Â Â Â Â Â Â Â  PR 23193
> Â Â Â Â Â Â Â  PR 19721
> Â Â Â Â Â Â Â  * aarch64-tbl.h: Use MOV (register) as an alias for ORR (shifted
> Â Â Â Â Â Â Â  register) iff shift == '00' && imm6 == '000000' && Rn == '11111'.
> 

Thanks for posting this.  I'm currently trying to find out whether or
not we want to continue accepting these extended MOV forms.  It's
certainly contrary to Arm ARM; but there are some other extensions that
we do deliberately accept for programmer convenience.

R.

> 
> Tested on aarch64-unknown-linux-gnu and showed no regressions.
> 
> Please take a look and apply if legitimate.
> 
> Regards,
> Egeyar
> 
> restrict-mov-alias-for-orr.patch
> 
> diff --git a/gas/testsuite/gas/aarch64/pr19721.d b/gas/testsuite/gas/aarch64/pr19721.d
> index a621ae5..785d2a2 100644
> --- a/gas/testsuite/gas/aarch64/pr19721.d
> +++ b/gas/testsuite/gas/aarch64/pr19721.d
> @@ -6,5 +6,8 @@ Disassembly of section \.text:
>  
>  0+000 <.*>:
>     0:	aa1103e7 	mov	x7, x17
> -   4:	aa1167e7 	mov	x7, x17, lsl #25
> -   8:	aa1167e7 	mov	x7, x17, lsl #25
> +   4:	aa1167e7 	orr	x7, xzr, x17, lsl #25
> +   8:	aa1167e7 	orr	x7, xzr, x17, lsl #25
> +   c:	aa4003e0 	orr	x0, xzr, x0, lsr #0
> +  10:	aa0007e0 	orr	x0, xzr, x0, lsl #1
> +  14:	aa0003d0 	orr	x16, x30, x0
> diff --git a/gas/testsuite/gas/aarch64/pr19721.s b/gas/testsuite/gas/aarch64/pr19721.s
> index cda068a..be2b508 100644
> --- a/gas/testsuite/gas/aarch64/pr19721.s
> +++ b/gas/testsuite/gas/aarch64/pr19721.s
> @@ -3,3 +3,6 @@
>  	mov	x7, x17
>  	mov	x7, x17, lsl 25
>  	orr	x7, xzr, x17, lsl 25
> +        orr     x0, xzr, x0, lsr #0	// shift == 01
> +        orr     x0, xzr, x0, lsl #1	// imm6 == 000001
> +        orr     x16, x30, x0		// Rn == 11110
> diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
> index b73007d..df56048 100644
> --- a/opcodes/aarch64-tbl.h
> +++ b/opcodes/aarch64-tbl.h
> @@ -3319,7 +3319,7 @@ struct aarch64_opcode aarch64_opcode_table[] =
>    CORE_INSN ("and", 0xa000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
>    CORE_INSN ("bic", 0xa200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_SF),
>    CORE_INSN ("orr", 0x2a000000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
> -  CORE_INSN ("mov", 0x2a0003e0, 0x7f2003e0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF),
> +  CORE_INSN ("mov", 0x2a0003e0, 0x7fe0ffe0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF),
>    CORE_INSN ("uxtw", 0x2a0003e0, 0x7f2003e0, log_shift, OP_UXTW, OP2 (Rd, Rm), QL_I2SAMEW, F_ALIAS | F_PSEUDO),
>    CORE_INSN ("orn", 0x2a200000, 0x7f200000, log_shift, 0, OP3 (Rd, Rn, Rm_SFT), QL_I3SAMER, F_HAS_ALIAS | F_SF),
>    CORE_INSN ("mvn", 0x2a2003e0, 0x7f2003e0, log_shift, 0, OP2 (Rd, Rm_SFT), QL_I2SAMER, F_ALIAS | F_SF),
>