[PATCH] RISC-V: Add fence.tso instruction

Jim Wilson jimw@sifive.com
Mon Oct 1 20:35:00 GMT 2018

On Mon, Oct 1, 2018 at 11:31 AM Palmer Dabbelt <palmer@sifive.com> wrote:
> The RISC-V memory model has been ratified, and it includes an additional
> fence: "fence.tso".  This pseudo instruction extends one of the
> previously reserved full fence patterns to be less restrictive, and
> therefor will execute correctly on all existing microarchitectures.
> Thus there is no reason to allow this instruction to be disabled (or
> unconverted to a full fence), so it's just unconditionally allowed.

The v2.2 ISA fence description says that reserved bits should be
ignored, so yes, this should be a safe forward compatible change.  I
see that the draft v2.3 ISA fence description adds a new field "fence
mode" (fm) which we aren't explicitly handling here, but there is no
way to set it other than via a fence.tso instruction, so it doesn't
look like we need explicit support for it.

This looks OK to me.


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