[PATCH] RISC-V: Add fence.tso instruction

Palmer Dabbelt palmer@sifive.com
Mon Oct 1 18:31:00 GMT 2018


The RISC-V memory model has been ratified, and it includes an additional
fence: "fence.tso".  This pseudo instruction extends one of the
previously reserved full fence patterns to be less restrictive, and
therefor will execute correctly on all existing microarchitectures.
Thus there is no reason to allow this instruction to be disabled (or
unconverted to a full fence), so it's just unconditionally allowed.

I've added a test case for GAS to check that "fence.tso" correctly
assembles on rv32i-based targets.  I checked to see that "fence.tso"
appears in "gas.log", but that's the only testing I've done.

gas/ChangeLog

2018-10-01  Palmer Dabbelt  <palmer@sifive.com>

        * testsuite/gas/riscv/fence-tso.d: New file.
        * testsuite/gas/riscv/fence-tso.s: Likewise.

include/ChangeLog

2018-10-01  Palmer Dabbelt  <palmer@sifive.com>

        * opcode/riscv-opc.h (MATCH_FENCE_TSO): New define.
        (MASK_FENCE_TSO): Likewise.

opcodes/ChangeLog

2018-10-01  Palmer Dabbelt  <palmer@sifive.com>

        * riscv-opc.c (riscv_opcodes) <fence.tso>: New opcode.
---
 gas/testsuite/gas/riscv/fence-tso.d | 11 +++++++++++
 gas/testsuite/gas/riscv/fence-tso.s |  2 ++
 include/opcode/riscv-opc.h          |  2 ++
 opcodes/riscv-opc.c                 |  1 +
 4 files changed, 16 insertions(+)
 create mode 100644 gas/testsuite/gas/riscv/fence-tso.d
 create mode 100644 gas/testsuite/gas/riscv/fence-tso.s

diff --git a/gas/testsuite/gas/riscv/fence-tso.d b/gas/testsuite/gas/riscv/fence-tso.d
new file mode 100644
index 000000000000..ef8a4cdd1c99
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fence-tso.d
@@ -0,0 +1,11 @@
+#as: -march=rv32ic
+#objdump: -dr
+
+.*:[ 	]+file format .*
+
+
+Disassembly of section .text:
+
+0+000 <target>:
+[ 	]+0:[ 	]+8330000f[ 	]+fence.tso
+
diff --git a/gas/testsuite/gas/riscv/fence-tso.s b/gas/testsuite/gas/riscv/fence-tso.s
new file mode 100644
index 000000000000..7770052b5e63
--- /dev/null
+++ b/gas/testsuite/gas/riscv/fence-tso.s
@@ -0,0 +1,2 @@
+target:
+	fence.tso
diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h
index 60bd2f999e8f..f09200c073d4 100644
--- a/include/opcode/riscv-opc.h
+++ b/include/opcode/riscv-opc.h
@@ -141,6 +141,8 @@
 #define MASK_FENCE  0x707f
 #define MATCH_FENCE_I 0x100f
 #define MASK_FENCE_I  0x707f
+#define MATCH_FENCE_TSO 0x8330000f
+#define MASK_FENCE_TSO  0xfff0707f
 #define MATCH_MUL 0x2000033
 #define MASK_MUL  0xfe00707f
 #define MATCH_MULH 0x2001033
diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c
index e0f711811f66..b6843f24373d 100644
--- a/opcodes/riscv-opc.c
+++ b/opcodes/riscv-opc.c
@@ -342,6 +342,7 @@ const struct riscv_opcode riscv_opcodes[] =
 {"fence",       0, {"I", 0},   "",  MATCH_FENCE | MASK_PRED | MASK_SUCC, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, INSN_ALIAS },
 {"fence",       0, {"I", 0},   "P,Q",  MATCH_FENCE, MASK_FENCE | MASK_RD | MASK_RS1 | (MASK_IMM & ~MASK_PRED & ~MASK_SUCC), match_opcode, 0 },
 {"fence.i",     0, {"I", 0},   "",  MATCH_FENCE_I, MASK_FENCE | MASK_RD | MASK_RS1 | MASK_IMM, match_opcode, 0 },
+{"fence.tso",   0, {"I", 0},   "",  MATCH_FENCE_TSO, MASK_FENCE_TSO | MASK_RD | MASK_RS1, match_opcode, INSN_ALIAS },
 {"rdcycle",     0, {"I", 0},   "d",  MATCH_RDCYCLE, MASK_RDCYCLE, match_opcode, INSN_ALIAS },
 {"rdinstret",   0, {"I", 0},   "d",  MATCH_RDINSTRET, MASK_RDINSTRET, match_opcode, INSN_ALIAS },
 {"rdtime",      0, {"I", 0},   "d",  MATCH_RDTIME, MASK_RDTIME, match_opcode, INSN_ALIAS },
-- 
2.16.4



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