[GAS][ARM][3/3]Add armv8.2 fp16 scalar instruction support. [Based on SE_H instruction shape for .f16, u16, s16, .16 type specifier]

[Renlin Li]

Hi all,

This patch add the armv8.2 fp16 scalar instructions into gas based on 
previous SE_H support.

The new armv8.2 fp16 scalar instructions are identified by the neon shape.
for example:
      vadd.f16 s0, s1, s2:        NS_HHH
      vabs.f16 s0, s1:              NS_HH
      vmov.f16 s0, r1:             NS_HR
      vmov.f16 r0, s1:             NS_RH

      vcvt.f16.s32    s2, s2, #29:    NS_HFI
      vcvt.u16.s32    s2, s2, #8:    NS_HFI

      vshl.u16 q3,q4,q5            NS_QQQ ---> not changed

If the SE_H is part of the shape, do_scalar_fp16_v82_encode function 
will be called
to change to coproc field to 9 to refection the encoding difference. The 
encoding of
the other parts is shared.

To be specific, the following instructions are added.

New VMOVX and VINS instructions are added to allow the extraction and 
insertion of the
upper 16 bits of a 32-bit vector register.
vins.f16
vmovx.f16

vabs.f16
vadd.f16
vcmp.f16
vcmpe.f16

VCVT (between floating-point and fixed-point)
vcvt.f16.s32
vcvt.f16.u32
vcvt.s32.f16
vcvt.u32.f16

VCVT (between floating-point and integer, both directions)
vcvt.s32.f16
vcvt.u32.f16
vcvt.f16.u32
vcvt.f16.s32

vcvta.u32.f16
vcvta.s32.f16
vcvtm.u32.f16
vcvtm.s32.f16
vcvtn.u32.f16
vcvtn.s32.f16
vcvtp.u32.f16
vcvtp.s32.f16
vcvtr.u32.f16
vcvtr.s32.f16

vdiv.f16
vfma.f16
vfms.f16
vfnma.f16
vfnms.f16
vmaxnm.f16
vminnm.f16
fmla.f16
vmls.f16

VMOV(between general-purpose register and half-precision register, 
immediate)
vmov.f16
vmov.f16

vmul.f16
vneg.f16
vnmla.f16
vnmls.f16
vnmul.f16

vrinta.f16
vrintm.f16
vrintn.f16
vrintp.f16
vrintr.f16
vrintx.f16
vrintz.f16

vseleq.f16
vselge.f16
vselgt.f16
vselvs.f16

vsqrt.f16
vsub.f16

load/store literal or address from register with optional offset
vldr.16
vstr.16

Binutils checked without any issues.


gas/ChangeLog:

2016-02-19  Renlin Li  <renlin.li@arm.com>

     * config/tc-arm.c (BAD_FP16): New error message macro.
     (do_scalar_fp16_v82_encode): Change the coproc field to 9 for armv8.2
     fp16 scalar instructions.
     (neon_check_type): Allow different size from key.
     (do_vfp_nsyn_add_sub): Add support SE_H shape support.
     (try_vfp_nsyn): Likewise.
     (do_vfp_nsyn_mla_mls): Likewise.
     (do_vfp_nsyn_fma_fms): Likewise.
     (do_vfp_nsyn_ldm_stm): Likewise
     (do_vfp_nsyn_sqrt): Likewise
     (do_vfp_nsyn_div): Likewise
     (do_vfp_nsyn_nmul): Likewise.
     (do_vfp_nsyn_cmp): Likewise.
     (do_neon_shll): Likewise.
     (do_vfp_nsyn_cvt_fpv8): Likewise.
     (do_neon_cvttb_2): Likewise.
     (do_neon_mov): Likewise.
     (do_neon_rshift_round_imm): Likewise.
     (do_neon_ldr_str): Likewise.
     (do_vfp_nsyn_fpv8): Likewise.
     (do_vmaxnm): Likewise.
     (do_vrint_1): Likewise.
     (insns): New entry for vins, vmovx.
     (md_apply_fix): Left shift 1 bit for fp16 vldr/vstr.
     * testsuite/gas/arm/armv8-2-fp16-scalar-thumb.d: New.
     * testsuite/gas/arm/armv8-2-fp16-scalar.d: New.
     * testsuite/gas/arm/armv8-2-fp16-scalar.s: New.
     * testsuite/gas/arm/armv8-2-fp16-scalar-bad.s: New
     * testsuite/gas/arm/armv8-2-fp16-scalar-bad.d: New
     * testsuite/gas/arm/armv8-2-fp16-scalar-bad.l: New


On 19/02/16 11:30, Renlin Li wrote:
> Hi all,
>
> This patch makes generic change to add a new neon shape SE_H to 
> represent VFP single
> precision register operand whose type specifier is .f16, .16, u16, s16.
>
> This will facilitate further patch to add ARMv8.2 fp16 instruction 
> support into GAS.
>
> for example, after the change, the new instruction share for the 
> following instruction is changed:
>
>          vcvtt.f16.f64  s0, d0:         NS_HD, instead of NS_FD
>          vcvtt.f64.f16  d0, s0:         NS_DH, instead of NS_DF
>          vcvtb s2.f16, s5.f32:          NS_HF, instead of NS_FF
>          vcvtb.f16.f32 s2, s5:          NS_HF, instead of NS_FF
>

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