[3/4, committed] Opcodes and assembler support for Nios II R2

[Sandra Loosemore]

This patch adds the new opcodes, assembler, and disassembler support
for Nios II R2.  This is a pretty gigantic patch, but there isn't a
good way to split it up into pieces.  As a brief roadmap:

The new file include/opcode/nios2r2.h has defines for all the new
instruction formats, fields, and opcodes.  The names are Altera's,
taken from the R2 processor documentation.

The R2 instruction syntax is in the new nios2_r2_opcodes array in
opcodes/nios2-opc.c.  Note that, unlike on some other targets that
support compressed instruction encodings, on Nios II the new 16-bit
CDX instructions are always explicitly designated, and the assembler
doesn't attempt to choose the best encoding automatically based on
command-line flags.  So, the assembly and disassembly implementation
generally still follows the same outline as for the existing R1 code,
driven by a descriptor string for each instruction that uses a letter
to describe the form and encoding of each argument.  There are a whole
pile of new argument descriptor letters (documented in
include/opcode/nios2.h), which require both assembler
(gas/config/tc-nios2.c) and disassembler (opcodes/nios2-dis.c)
support.  Likewise the assembler/disassembler are both extended to
know about the new R2 instruction formats for the argument letters
already used for the R1 instruction subset.

There are some other random bits like support for swapping in the
right instruction tables for the mach variant, mappings for the new R2
fields that are defined as enumerations, branch relaxation support,
handling for the new alignment and padding behavior, etc.

The R2 assembler test cases will be posted as a separate patch.

-Sandra
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