[PATCH] Add Octeon CP0 names to the disassembler

[David Daney]

On 12/06/2011 04:01 PM, Andrew Pinski wrote:
> Hi,
>    This patch adds the CP0 names to the disassembler just like there
> are ones for XLR.
> OK?  Tested for mips64-linux-gnu with no regressions.
>
> Thanks,
> Andrew Pinski
>
> gas/testsuite/ChangeLog:
> * gas/mips/cp0-names-octeon.d: New file
> * gas/mips/cp0sel-names-octeon.d: Likewise.
> * gas/mips/mips.exp: Run cp0-names-octeon and cp0sel-names-octeon.
>
> opcodes/ChangeLog:
> * mips-dis.c (mips_cp0_names_octeon): Define.
> (mips_cp0sel_names_octeon): Define.
> (mips_arch_choices): Change Octeon and Octeon+ to use
> mips_cp0_names_octeon and mips_cp0sel_names_octeon.
>
>
[...]
>
> +/* Octeon cop0 register names.  */
> +static const char * const mips_cp0_names_octeon[32] = {
> +  "c0_index",     "c0_random",    "c0_entrylo0",  "c0_entrylo1",
> +  "c0_context",   "c0_pagemask",  "c0_wired",     "c0_hwrena",
> +  "c0_badvaddr",  "c0_count",     "c0_entryhi",   "c0_compare",
> +  "c0_status",    "c0_cause",     "c0_epc",       "c0_prid",
> +  "c0_config",    "$17",          "c0_watchlo",   "c0_watchhi",
> +  "c0_xcontext",  "$21",          "c0_mdebug",    "c0_debug",
> +  "c0_depc",      "c0_perfctl0",   "$26",         "c0_cacheerri",
> +  "c0_tagloi",    "c0_taghii",     "c0_errorepc",  "c0_desave",
> +};
> +
> +/* Octeon's CP0 Select Registers.  */
> +static const struct mips_cp0sel_name mips_cp0sel_names_octeon[] = {
> +  { 5,  1, "c0_pagegrain"	},
> +  { 9,  6, "c0_cvmcount"	},
> +  { 9,  7, "c0_cvmctl"		},
> +  { 11, 7, "c0_cvmmemctl"	},
> +  { 12, 1, "c0_intctl"		},
> +  { 12, 2, "c0_srsctl"		},
> +  { 15, 1, "c0_ebase"		},
> +  { 16, 1, "c0_config1"		},
> +  { 16, 2, "c0_config2"		},
> +  { 16, 3, "c0_config3"		},
> +  { 18, 1, "c0_watchlo1"	},
> +  { 19, 1, "c0_watchhi1"	},
> +  { 25, 1, "c0_perfval0"	},
> +  { 25, 2, "c0_perfctl1"	},
> +  { 25, 3, "c0_perfval1"	},
> +  { 27, 1, "c0_cacheerrd"	},
> +  { 28, 1, "c0_dataloi"		},
> +  { 28, 2, "c0_taglod"		},
> +  { 28, 3, "c0_datalod"		},
> +  { 29, 1, "c0_datahii"		},
> +  { 29, 2, "c0_taghid"		},
> +  { 29, 3, "c0_datahid"		},
> +};
> +

The vast majority of these registers are defined in the mips{32,64}r3 
architecture reference manual.

It seems like we should find a way to factor out all the common things, 
and only supply overrides for register/select values that are 'Reserved 
for Implementations'

David Daney