[PATCH] Add Octeon CP0 names to the disassembler
Andrew Pinski
pinskia@gmail.com
Wed Dec 7 00:02:00 GMT 2011
Hi,
This patch adds the CP0 names to the disassembler just like there
are ones for XLR.
OK? Tested for mips64-linux-gnu with no regressions.
Thanks,
Andrew Pinski
gas/testsuite/ChangeLog:
* gas/mips/cp0-names-octeon.d: New file
* gas/mips/cp0sel-names-octeon.d: Likewise.
* gas/mips/mips.exp: Run cp0-names-octeon and cp0sel-names-octeon.
opcodes/ChangeLog:
* mips-dis.c (mips_cp0_names_octeon): Define.
(mips_cp0sel_names_octeon): Define.
(mips_arch_choices): Change Octeon and Octeon+ to use
mips_cp0_names_octeon and mips_cp0sel_names_octeon.
-------------- next part --------------
Index: gas/testsuite/gas/mips/cp0-names-octeon.d
===================================================================
RCS file: gas/testsuite/gas/mips/cp0-names-octeon.d
diff -N gas/testsuite/gas/mips/cp0-names-octeon.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/cp0-names-octeon.d 6 Dec 2011 23:55:10 -0000
@@ -0,0 +1,42 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -M gpr-names=numeric,cp0-names=octeon
+#name: MIPS CP0 register disassembly (octeon)
+#source: cp0-names.s
+
+# Check objdump's handling of -M cp0-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 40800000 mtc0 \$0,c0_index
+0+0004 <[^>]*> 40800800 mtc0 \$0,c0_random
+0+0008 <[^>]*> 40801000 mtc0 \$0,c0_entrylo0
+0+000c <[^>]*> 40801800 mtc0 \$0,c0_entrylo1
+0+0010 <[^>]*> 40802000 mtc0 \$0,c0_context
+0+0014 <[^>]*> 40802800 mtc0 \$0,c0_pagemask
+0+0018 <[^>]*> 40803000 mtc0 \$0,c0_wired
+0+001c <[^>]*> 40803800 mtc0 \$0,c0_hwrena
+0+0020 <[^>]*> 40804000 mtc0 \$0,c0_badvaddr
+0+0024 <[^>]*> 40804800 mtc0 \$0,c0_count
+0+0028 <[^>]*> 40805000 mtc0 \$0,c0_entryhi
+0+002c <[^>]*> 40805800 mtc0 \$0,c0_compare
+0+0030 <[^>]*> 40806000 mtc0 \$0,c0_status
+0+0034 <[^>]*> 40806800 mtc0 \$0,c0_cause
+0+0038 <[^>]*> 40807000 mtc0 \$0,c0_epc
+0+003c <[^>]*> 40807800 mtc0 \$0,c0_prid
+0+0040 <[^>]*> 40808000 mtc0 \$0,c0_config
+0+0044 <[^>]*> 40808800 mtc0 \$0,\$17
+0+0048 <[^>]*> 40809000 mtc0 \$0,c0_watchlo
+0+004c <[^>]*> 40809800 mtc0 \$0,c0_watchhi
+0+0050 <[^>]*> 4080a000 mtc0 \$0,c0_xcontext
+0+0054 <[^>]*> 4080a800 mtc0 \$0,\$21
+0+0058 <[^>]*> 4080b000 mtc0 \$0,c0_mdebug
+0+005c <[^>]*> 4080b800 mtc0 \$0,c0_debug
+0+0060 <[^>]*> 4080c000 mtc0 \$0,c0_depc
+0+0064 <[^>]*> 4080c800 mtc0 \$0,c0_perfctl0
+0+0068 <[^>]*> 4080d000 mtc0 \$0,\$26
+0+006c <[^>]*> 4080d800 mtc0 \$0,c0_cacheerri
+0+0070 <[^>]*> 4080e000 mtc0 \$0,c0_tagloi
+0+0074 <[^>]*> 4080e800 mtc0 \$0,c0_taghii
+0+0078 <[^>]*> 4080f000 mtc0 \$0,c0_errorepc
+0+007c <[^>]*> 4080f800 mtc0 \$0,c0_desave
+ \.\.\.
Index: gas/testsuite/gas/mips/cp0sel-names-octeon.d
===================================================================
RCS file: gas/testsuite/gas/mips/cp0sel-names-octeon.d
diff -N gas/testsuite/gas/mips/cp0sel-names-octeon.d
--- /dev/null 1 Jan 1970 00:00:00 -0000
+++ gas/testsuite/gas/mips/cp0sel-names-octeon.d 6 Dec 2011 23:55:10 -0000
@@ -0,0 +1,235 @@
+#objdump: -dr --prefix-addresses --show-raw-insn -mmips:isa32 -M gpr-names=numeric,cp0-names=octeon
+#name: MIPS CP0 with sel register disassembly (octeon)
+#as: -32 -march=mips32
+#source: cp0sel-names.s
+
+# Check objdump's handling of -M cp0-names=foo options.
+
+.*: +file format .*mips.*
+
+Disassembly of section .text:
+0+0000 <[^>]*> 40800001 mtc0 \$0,\$0,1
+0+0004 <[^>]*> 40800002 mtc0 \$0,\$0,2
+0+0008 <[^>]*> 40800003 mtc0 \$0,\$0,3
+0+000c <[^>]*> 40800004 mtc0 \$0,\$0,4
+0+0010 <[^>]*> 40800005 mtc0 \$0,\$0,5
+0+0014 <[^>]*> 40800006 mtc0 \$0,\$0,6
+0+0018 <[^>]*> 40800007 mtc0 \$0,\$0,7
+0+001c <[^>]*> 40800801 mtc0 \$0,\$1,1
+0+0020 <[^>]*> 40800802 mtc0 \$0,\$1,2
+0+0024 <[^>]*> 40800803 mtc0 \$0,\$1,3
+0+0028 <[^>]*> 40800804 mtc0 \$0,\$1,4
+0+002c <[^>]*> 40800805 mtc0 \$0,\$1,5
+0+0030 <[^>]*> 40800806 mtc0 \$0,\$1,6
+0+0034 <[^>]*> 40800807 mtc0 \$0,\$1,7
+0+0038 <[^>]*> 40801001 mtc0 \$0,\$2,1
+0+003c <[^>]*> 40801002 mtc0 \$0,\$2,2
+0+0040 <[^>]*> 40801003 mtc0 \$0,\$2,3
+0+0044 <[^>]*> 40801004 mtc0 \$0,\$2,4
+0+0048 <[^>]*> 40801005 mtc0 \$0,\$2,5
+0+004c <[^>]*> 40801006 mtc0 \$0,\$2,6
+0+0050 <[^>]*> 40801007 mtc0 \$0,\$2,7
+0+0054 <[^>]*> 40801801 mtc0 \$0,\$3,1
+0+0058 <[^>]*> 40801802 mtc0 \$0,\$3,2
+0+005c <[^>]*> 40801803 mtc0 \$0,\$3,3
+0+0060 <[^>]*> 40801804 mtc0 \$0,\$3,4
+0+0064 <[^>]*> 40801805 mtc0 \$0,\$3,5
+0+0068 <[^>]*> 40801806 mtc0 \$0,\$3,6
+0+006c <[^>]*> 40801807 mtc0 \$0,\$3,7
+0+0070 <[^>]*> 40802001 mtc0 \$0,\$4,1
+0+0074 <[^>]*> 40802002 mtc0 \$0,\$4,2
+0+0078 <[^>]*> 40802003 mtc0 \$0,\$4,3
+0+007c <[^>]*> 40802004 mtc0 \$0,\$4,4
+0+0080 <[^>]*> 40802005 mtc0 \$0,\$4,5
+0+0084 <[^>]*> 40802006 mtc0 \$0,\$4,6
+0+0088 <[^>]*> 40802007 mtc0 \$0,\$4,7
+0+008c <[^>]*> 40802801 mtc0 \$0,c0_pagegrain
+0+0090 <[^>]*> 40802802 mtc0 \$0,\$5,2
+0+0094 <[^>]*> 40802803 mtc0 \$0,\$5,3
+0+0098 <[^>]*> 40802804 mtc0 \$0,\$5,4
+0+009c <[^>]*> 40802805 mtc0 \$0,\$5,5
+0+00a0 <[^>]*> 40802806 mtc0 \$0,\$5,6
+0+00a4 <[^>]*> 40802807 mtc0 \$0,\$5,7
+0+00a8 <[^>]*> 40803001 mtc0 \$0,\$6,1
+0+00ac <[^>]*> 40803002 mtc0 \$0,\$6,2
+0+00b0 <[^>]*> 40803003 mtc0 \$0,\$6,3
+0+00b4 <[^>]*> 40803004 mtc0 \$0,\$6,4
+0+00b8 <[^>]*> 40803005 mtc0 \$0,\$6,5
+0+00bc <[^>]*> 40803006 mtc0 \$0,\$6,6
+0+00c0 <[^>]*> 40803007 mtc0 \$0,\$6,7
+0+00c4 <[^>]*> 40803801 mtc0 \$0,\$7,1
+0+00c8 <[^>]*> 40803802 mtc0 \$0,\$7,2
+0+00cc <[^>]*> 40803803 mtc0 \$0,\$7,3
+0+00d0 <[^>]*> 40803804 mtc0 \$0,\$7,4
+0+00d4 <[^>]*> 40803805 mtc0 \$0,\$7,5
+0+00d8 <[^>]*> 40803806 mtc0 \$0,\$7,6
+0+00dc <[^>]*> 40803807 mtc0 \$0,\$7,7
+0+00e0 <[^>]*> 40804001 mtc0 \$0,\$8,1
+0+00e4 <[^>]*> 40804002 mtc0 \$0,\$8,2
+0+00e8 <[^>]*> 40804003 mtc0 \$0,\$8,3
+0+00ec <[^>]*> 40804004 mtc0 \$0,\$8,4
+0+00f0 <[^>]*> 40804005 mtc0 \$0,\$8,5
+0+00f4 <[^>]*> 40804006 mtc0 \$0,\$8,6
+0+00f8 <[^>]*> 40804007 mtc0 \$0,\$8,7
+0+00fc <[^>]*> 40804801 mtc0 \$0,\$9,1
+0+0100 <[^>]*> 40804802 mtc0 \$0,\$9,2
+0+0104 <[^>]*> 40804803 mtc0 \$0,\$9,3
+0+0108 <[^>]*> 40804804 mtc0 \$0,\$9,4
+0+010c <[^>]*> 40804805 mtc0 \$0,\$9,5
+0+0110 <[^>]*> 40804806 mtc0 \$0,c0_cvmcount
+0+0114 <[^>]*> 40804807 mtc0 \$0,c0_cvmctl
+0+0118 <[^>]*> 40805001 mtc0 \$0,\$10,1
+0+011c <[^>]*> 40805002 mtc0 \$0,\$10,2
+0+0120 <[^>]*> 40805003 mtc0 \$0,\$10,3
+0+0124 <[^>]*> 40805004 mtc0 \$0,\$10,4
+0+0128 <[^>]*> 40805005 mtc0 \$0,\$10,5
+0+012c <[^>]*> 40805006 mtc0 \$0,\$10,6
+0+0130 <[^>]*> 40805007 mtc0 \$0,\$10,7
+0+0134 <[^>]*> 40805801 mtc0 \$0,\$11,1
+0+0138 <[^>]*> 40805802 mtc0 \$0,\$11,2
+0+013c <[^>]*> 40805803 mtc0 \$0,\$11,3
+0+0140 <[^>]*> 40805804 mtc0 \$0,\$11,4
+0+0144 <[^>]*> 40805805 mtc0 \$0,\$11,5
+0+0148 <[^>]*> 40805806 mtc0 \$0,\$11,6
+0+014c <[^>]*> 40805807 mtc0 \$0,c0_cvmmemctl
+0+0150 <[^>]*> 40806001 mtc0 \$0,c0_intctl
+0+0154 <[^>]*> 40806002 mtc0 \$0,c0_srsctl
+0+0158 <[^>]*> 40806003 mtc0 \$0,\$12,3
+0+015c <[^>]*> 40806004 mtc0 \$0,\$12,4
+0+0160 <[^>]*> 40806005 mtc0 \$0,\$12,5
+0+0164 <[^>]*> 40806006 mtc0 \$0,\$12,6
+0+0168 <[^>]*> 40806007 mtc0 \$0,\$12,7
+0+016c <[^>]*> 40806801 mtc0 \$0,\$13,1
+0+0170 <[^>]*> 40806802 mtc0 \$0,\$13,2
+0+0174 <[^>]*> 40806803 mtc0 \$0,\$13,3
+0+0178 <[^>]*> 40806804 mtc0 \$0,\$13,4
+0+017c <[^>]*> 40806805 mtc0 \$0,\$13,5
+0+0180 <[^>]*> 40806806 mtc0 \$0,\$13,6
+0+0184 <[^>]*> 40806807 mtc0 \$0,\$13,7
+0+0188 <[^>]*> 40807001 mtc0 \$0,\$14,1
+0+018c <[^>]*> 40807002 mtc0 \$0,\$14,2
+0+0190 <[^>]*> 40807003 mtc0 \$0,\$14,3
+0+0194 <[^>]*> 40807004 mtc0 \$0,\$14,4
+0+0198 <[^>]*> 40807005 mtc0 \$0,\$14,5
+0+019c <[^>]*> 40807006 mtc0 \$0,\$14,6
+0+01a0 <[^>]*> 40807007 mtc0 \$0,\$14,7
+0+01a4 <[^>]*> 40807801 mtc0 \$0,c0_ebase
+0+01a8 <[^>]*> 40807802 mtc0 \$0,\$15,2
+0+01ac <[^>]*> 40807803 mtc0 \$0,\$15,3
+0+01b0 <[^>]*> 40807804 mtc0 \$0,\$15,4
+0+01b4 <[^>]*> 40807805 mtc0 \$0,\$15,5
+0+01b8 <[^>]*> 40807806 mtc0 \$0,\$15,6
+0+01bc <[^>]*> 40807807 mtc0 \$0,\$15,7
+0+01c0 <[^>]*> 40808001 mtc0 \$0,c0_config1
+0+01c4 <[^>]*> 40808002 mtc0 \$0,c0_config2
+0+01c8 <[^>]*> 40808003 mtc0 \$0,c0_config3
+0+01cc <[^>]*> 40808004 mtc0 \$0,\$16,4
+0+01d0 <[^>]*> 40808005 mtc0 \$0,\$16,5
+0+01d4 <[^>]*> 40808006 mtc0 \$0,\$16,6
+0+01d8 <[^>]*> 40808007 mtc0 \$0,\$16,7
+0+01dc <[^>]*> 40808801 mtc0 \$0,\$17,1
+0+01e0 <[^>]*> 40808802 mtc0 \$0,\$17,2
+0+01e4 <[^>]*> 40808803 mtc0 \$0,\$17,3
+0+01e8 <[^>]*> 40808804 mtc0 \$0,\$17,4
+0+01ec <[^>]*> 40808805 mtc0 \$0,\$17,5
+0+01f0 <[^>]*> 40808806 mtc0 \$0,\$17,6
+0+01f4 <[^>]*> 40808807 mtc0 \$0,\$17,7
+0+01f8 <[^>]*> 40809001 mtc0 \$0,c0_watchlo1
+0+01fc <[^>]*> 40809002 mtc0 \$0,\$18,2
+0+0200 <[^>]*> 40809003 mtc0 \$0,\$18,3
+0+0204 <[^>]*> 40809004 mtc0 \$0,\$18,4
+0+0208 <[^>]*> 40809005 mtc0 \$0,\$18,5
+0+020c <[^>]*> 40809006 mtc0 \$0,\$18,6
+0+0210 <[^>]*> 40809007 mtc0 \$0,\$18,7
+0+0214 <[^>]*> 40809801 mtc0 \$0,c0_watchhi1
+0+0218 <[^>]*> 40809802 mtc0 \$0,\$19,2
+0+021c <[^>]*> 40809803 mtc0 \$0,\$19,3
+0+0220 <[^>]*> 40809804 mtc0 \$0,\$19,4
+0+0224 <[^>]*> 40809805 mtc0 \$0,\$19,5
+0+0228 <[^>]*> 40809806 mtc0 \$0,\$19,6
+0+022c <[^>]*> 40809807 mtc0 \$0,\$19,7
+0+0230 <[^>]*> 4080a001 mtc0 \$0,\$20,1
+0+0234 <[^>]*> 4080a002 mtc0 \$0,\$20,2
+0+0238 <[^>]*> 4080a003 mtc0 \$0,\$20,3
+0+023c <[^>]*> 4080a004 mtc0 \$0,\$20,4
+0+0240 <[^>]*> 4080a005 mtc0 \$0,\$20,5
+0+0244 <[^>]*> 4080a006 mtc0 \$0,\$20,6
+0+0248 <[^>]*> 4080a007 mtc0 \$0,\$20,7
+0+024c <[^>]*> 4080a801 mtc0 \$0,\$21,1
+0+0250 <[^>]*> 4080a802 mtc0 \$0,\$21,2
+0+0254 <[^>]*> 4080a803 mtc0 \$0,\$21,3
+0+0258 <[^>]*> 4080a804 mtc0 \$0,\$21,4
+0+025c <[^>]*> 4080a805 mtc0 \$0,\$21,5
+0+0260 <[^>]*> 4080a806 mtc0 \$0,\$21,6
+0+0264 <[^>]*> 4080a807 mtc0 \$0,\$21,7
+0+0268 <[^>]*> 4080b001 mtc0 \$0,\$22,1
+0+026c <[^>]*> 4080b002 mtc0 \$0,\$22,2
+0+0270 <[^>]*> 4080b003 mtc0 \$0,\$22,3
+0+0274 <[^>]*> 4080b004 mtc0 \$0,\$22,4
+0+0278 <[^>]*> 4080b005 mtc0 \$0,\$22,5
+0+027c <[^>]*> 4080b006 mtc0 \$0,\$22,6
+0+0280 <[^>]*> 4080b007 mtc0 \$0,\$22,7
+0+0284 <[^>]*> 4080b801 mtc0 \$0,\$23,1
+0+0288 <[^>]*> 4080b802 mtc0 \$0,\$23,2
+0+028c <[^>]*> 4080b803 mtc0 \$0,\$23,3
+0+0290 <[^>]*> 4080b804 mtc0 \$0,\$23,4
+0+0294 <[^>]*> 4080b805 mtc0 \$0,\$23,5
+0+0298 <[^>]*> 4080b806 mtc0 \$0,\$23,6
+0+029c <[^>]*> 4080b807 mtc0 \$0,\$23,7
+0+02a0 <[^>]*> 4080c001 mtc0 \$0,\$24,1
+0+02a4 <[^>]*> 4080c002 mtc0 \$0,\$24,2
+0+02a8 <[^>]*> 4080c003 mtc0 \$0,\$24,3
+0+02ac <[^>]*> 4080c004 mtc0 \$0,\$24,4
+0+02b0 <[^>]*> 4080c005 mtc0 \$0,\$24,5
+0+02b4 <[^>]*> 4080c006 mtc0 \$0,\$24,6
+0+02b8 <[^>]*> 4080c007 mtc0 \$0,\$24,7
+0+02bc <[^>]*> 4080c801 mtc0 \$0,c0_perfval0
+0+02c0 <[^>]*> 4080c802 mtc0 \$0,c0_perfctl1
+0+02c4 <[^>]*> 4080c803 mtc0 \$0,c0_perfval1
+0+02c8 <[^>]*> 4080c804 mtc0 \$0,\$25,4
+0+02cc <[^>]*> 4080c805 mtc0 \$0,\$25,5
+0+02d0 <[^>]*> 4080c806 mtc0 \$0,\$25,6
+0+02d4 <[^>]*> 4080c807 mtc0 \$0,\$25,7
+0+02d8 <[^>]*> 4080d001 mtc0 \$0,\$26,1
+0+02dc <[^>]*> 4080d002 mtc0 \$0,\$26,2
+0+02e0 <[^>]*> 4080d003 mtc0 \$0,\$26,3
+0+02e4 <[^>]*> 4080d004 mtc0 \$0,\$26,4
+0+02e8 <[^>]*> 4080d005 mtc0 \$0,\$26,5
+0+02ec <[^>]*> 4080d006 mtc0 \$0,\$26,6
+0+02f0 <[^>]*> 4080d007 mtc0 \$0,\$26,7
+0+02f4 <[^>]*> 4080d801 mtc0 \$0,c0_cacheerrd
+0+02f8 <[^>]*> 4080d802 mtc0 \$0,\$27,2
+0+02fc <[^>]*> 4080d803 mtc0 \$0,\$27,3
+0+0300 <[^>]*> 4080d804 mtc0 \$0,\$27,4
+0+0304 <[^>]*> 4080d805 mtc0 \$0,\$27,5
+0+0308 <[^>]*> 4080d806 mtc0 \$0,\$27,6
+0+030c <[^>]*> 4080d807 mtc0 \$0,\$27,7
+0+0310 <[^>]*> 4080e001 mtc0 \$0,c0_dataloi
+0+0314 <[^>]*> 4080e002 mtc0 \$0,c0_taglod
+0+0318 <[^>]*> 4080e003 mtc0 \$0,c0_datalod
+0+031c <[^>]*> 4080e004 mtc0 \$0,\$28,4
+0+0320 <[^>]*> 4080e005 mtc0 \$0,\$28,5
+0+0324 <[^>]*> 4080e006 mtc0 \$0,\$28,6
+0+0328 <[^>]*> 4080e007 mtc0 \$0,\$28,7
+0+032c <[^>]*> 4080e801 mtc0 \$0,c0_datahii
+0+0330 <[^>]*> 4080e802 mtc0 \$0,c0_taghid
+0+0334 <[^>]*> 4080e803 mtc0 \$0,c0_datahid
+0+0338 <[^>]*> 4080e804 mtc0 \$0,\$29,4
+0+033c <[^>]*> 4080e805 mtc0 \$0,\$29,5
+0+0340 <[^>]*> 4080e806 mtc0 \$0,\$29,6
+0+0344 <[^>]*> 4080e807 mtc0 \$0,\$29,7
+0+0348 <[^>]*> 4080f001 mtc0 \$0,\$30,1
+0+034c <[^>]*> 4080f002 mtc0 \$0,\$30,2
+0+0350 <[^>]*> 4080f003 mtc0 \$0,\$30,3
+0+0354 <[^>]*> 4080f004 mtc0 \$0,\$30,4
+0+0358 <[^>]*> 4080f005 mtc0 \$0,\$30,5
+0+035c <[^>]*> 4080f006 mtc0 \$0,\$30,6
+0+0360 <[^>]*> 4080f007 mtc0 \$0,\$30,7
+0+0364 <[^>]*> 4080f801 mtc0 \$0,\$31,1
+0+0368 <[^>]*> 4080f802 mtc0 \$0,\$31,2
+0+036c <[^>]*> 4080f803 mtc0 \$0,\$31,3
+0+0370 <[^>]*> 4080f804 mtc0 \$0,\$31,4
+0+0374 <[^>]*> 4080f805 mtc0 \$0,\$31,5
+0+0378 <[^>]*> 4080f806 mtc0 \$0,\$31,6
+0+037c <[^>]*> 4080f807 mtc0 \$0,\$31,7
+ \.\.\.
Index: gas/testsuite/gas/mips/mips.exp
===================================================================
RCS file: /cvs/src/src/gas/testsuite/gas/mips/mips.exp,v
retrieving revision 1.196
diff -u -p -r1.196 mips.exp
--- gas/testsuite/gas/mips/mips.exp 3 Dec 2011 10:29:53 -0000 1.196
+++ gas/testsuite/gas/mips/mips.exp 6 Dec 2011 23:55:10 -0000
@@ -951,6 +951,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "cp0-names-mips32r2"
run_dump_test "cp0-names-mips64"
run_dump_test "cp0-names-mips64r2"
+ run_dump_test "cp0-names-octeon"
run_dump_test "cp0-names-sb1"
run_dump_test "cp0sel-names-numeric"
@@ -958,6 +959,7 @@ if { [istarget mips*-*-vxworks*] } {
run_dump_test "cp0sel-names-mips32r2"
run_dump_test "cp0sel-names-mips64"
run_dump_test "cp0sel-names-mips64r2"
+ run_dump_test "cp0sel-names-octeon"
run_dump_test "cp0sel-names-sb1"
run_dump_test "hwr-names-numeric"
Index: opcodes/mips-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mips-dis.c,v
retrieving revision 1.88
diff -u -p -r1.88 mips-dis.c
--- opcodes/mips-dis.c 29 Nov 2011 20:28:55 -0000 1.88
+++ opcodes/mips-dis.c 6 Dec 2011 23:55:10 -0000
@@ -404,6 +404,44 @@ static const struct mips_cp0sel_name mip
{ 29, 3, "c0_datahi_d" },
};
+/* Octeon cop0 register names. */
+static const char * const mips_cp0_names_octeon[32] = {
+ "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
+ "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
+ "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
+ "c0_status", "c0_cause", "c0_epc", "c0_prid",
+ "c0_config", "$17", "c0_watchlo", "c0_watchhi",
+ "c0_xcontext", "$21", "c0_mdebug", "c0_debug",
+ "c0_depc", "c0_perfctl0", "$26", "c0_cacheerri",
+ "c0_tagloi", "c0_taghii", "c0_errorepc", "c0_desave",
+};
+
+/* Octeon's CP0 Select Registers. */
+static const struct mips_cp0sel_name mips_cp0sel_names_octeon[] = {
+ { 5, 1, "c0_pagegrain" },
+ { 9, 6, "c0_cvmcount" },
+ { 9, 7, "c0_cvmctl" },
+ { 11, 7, "c0_cvmmemctl" },
+ { 12, 1, "c0_intctl" },
+ { 12, 2, "c0_srsctl" },
+ { 15, 1, "c0_ebase" },
+ { 16, 1, "c0_config1" },
+ { 16, 2, "c0_config2" },
+ { 16, 3, "c0_config3" },
+ { 18, 1, "c0_watchlo1" },
+ { 19, 1, "c0_watchhi1" },
+ { 25, 1, "c0_perfval0" },
+ { 25, 2, "c0_perfctl1" },
+ { 25, 3, "c0_perfval1" },
+ { 27, 1, "c0_cacheerrd" },
+ { 28, 1, "c0_dataloi" },
+ { 28, 2, "c0_taglod" },
+ { 28, 3, "c0_datalod" },
+ { 29, 1, "c0_datahii" },
+ { 29, 2, "c0_taghid" },
+ { 29, 3, "c0_datahid" },
+};
+
/* Xlr cop0 register names. */
static const char * const mips_cp0_names_xlr[32] = {
"c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
@@ -602,12 +640,14 @@ const struct mips_arch_choice mips_arch_
NULL, 0, mips_hwr_names_numeric },
{ "octeon", 1, bfd_mach_mips_octeon, CPU_OCTEON,
- ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_numeric, NULL, 0,
+ ISA_MIPS64R2 | INSN_OCTEON, mips_cp0_names_octeon,
+ mips_cp0sel_names_octeon, ARRAY_SIZE (mips_cp0sel_names_octeon),
mips_hwr_names_numeric },
{ "octeon+", 1, bfd_mach_mips_octeonp, CPU_OCTEONP,
- ISA_MIPS64R2 | INSN_OCTEON | INSN_OCTEONP, mips_cp0_names_numeric,
- NULL, 0, mips_hwr_names_numeric },
+ ISA_MIPS64R2 | INSN_OCTEON | INSN_OCTEONP, mips_cp0_names_octeon,
+ mips_cp0sel_names_octeon, ARRAY_SIZE (mips_cp0sel_names_octeon),
+ mips_hwr_names_numeric },
{ "xlr", 1, bfd_mach_mips_xlr, CPU_XLR,
ISA_MIPS64 | INSN_XLR,
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