[PATCH] Add LWP support for upcoming AMD Orochi processor

[H.J. Lu]

On Thu, Nov 5, 2009 at 3:12 PM, H.J. Lu <hjl.tools@gmail.com> wrote:
> On Thu, Nov 5, 2009 at 3:52 PM, Sebastian Pop <sebpop@gmail.com> wrote:
>> Hi,
>>
>> On Thu, Nov 5, 2009 at 15:45, H.J. Lu <hjl.tools@gmail.com> wrote:
>>> There is no 32bit LWP test. Is LWP 64bit only? If yes, you need to
>>> add Cpu64 to LWP insns.
>>>
>>> Also please update doc/c-i386.texi.
>>>
>
> Please document the new .lwd directive. OK with this change.
>
> Thanks.
>
>
> H.J.
> ---
>> LWP is supported both in 64 and 32 bit modes.
>> Fixed like this:
>>
>> 2009-11-05  Sebastian Pop  <sebastian.pop@amd.com>
>>            Quentin Neill  <quentin.neill@amd.com>
>>
>>        * gas/config/tc-i386.c (cpu_arch): Add CPU_LWP_FLAGS.
>>        (build_vex_prefix): Handle xop09 and xop0a.
>>        (build_modrm_byte): Handle vexlwp.
>>        (md_show_usage): Add lwp.
>>        * gas/doc/c-i386.texi (i386-LWP): New section.
>>
>>        * gas/testsuite/gas/i386/i386.exp: Run x86-64-lwp in 64-bit mode,
>>        run lwp in 32-bit mode.
>>        * gas/testsuite/gas/i386/x86-64-lwp.d: New.
>>        * gas/testsuite/gas/i386/x86-64-lwp.s: New.
>>        * gas/testsuite/gas/i386/lwp.d: New.
>>        * gas/testsuite/gas/i386/lwp.s: New.
>>
>>        * opcodes/i386-dis.c (OP_LWPCB_E): New.
>>        (OP_LWP_E): New.
>>        (OP_LWP_I): New.
>>        (USE_XOP_8F_TABLE): New.
>>        (XOP_8F_TABLE): New.
>>        (REG_XOP_LWPCB): New.
>>        (REG_XOP_LWP): New.
>>        (XOP_09): New.
>>        (XOP_0A): New.
>>        (reg_table): Redirect REG_8F to XOP_8F_TABLE.
>>        Add entries for REG_XOP_LWPCB and REG_XOP_LWP.
>>        (xop_table): New.
>>        (get_valid_dis386): Handle USE_XOP_8F_TABLE.
>>        Use the offsets VEX_0F, VEX_0F38, and VEX_0F3A instead of their values
>>        to access to the vex_table.
>>        (OP_LWPCB_E): New.
>>        (OP_LWP_E): New.
>>        (OP_LWP_I): New.
>>        * opcodes/i386-gen.c (cpu_flag_init): Add CPU_LWP_FLAGS, CpuLWP.
>>        (cpu_flags): Add CpuLWP.
>>        (opcode_modifiers): Add VexLWP, XOP09, and XOP0A.
>>        * opcodes/i386-opc.h (CpuLWP): New.
>>        (i386_cpu_flags): Add bit cpulwp.
>>        (VexLWP): New.
>>        (XOP09): New.
>>        (XOP0A): New.
>>        (i386_opcode_modifier): Add vexlwp, xop09, and xop0a.
>>        * opcodes/i386-opc.tbl (llwpcb): Added.
>>        (lwpval): Added.
>>        (lwpins): Added.
>>
>> Tested on x86-64-linux with make -k check.
>> Ok to commit?
>>
>> Thanks,
>> Sebastian Pop
>> --
>> AMD / Open Source Compiler Engineering / GNU Tools
>>
>
>

I checked in this patch to group AMD options together.


-- 
H.J.
--
diff --git a/gas/doc/c-i386.texi b/gas/doc/c-i386.texi
index 9dacf4c..5661f75 100644
--- a/gas/doc/c-i386.texi
+++ b/gas/doc/c-i386.texi
@@ -919,9 +919,10 @@ supported on the CPU specified.  The choices for @var{cpu_t
ype} are:
 @item @samp{.ssse3} @tab @samp{.sse4.1} @tab @samp{.sse4.2} @tab @samp{.sse4}
 @item @samp{.avx} @tab @samp{.vmx} @tab @samp{.smx} @tab @samp{.xsave}
 @item @samp{.aes} @tab @samp{.pclmul} @tab @samp{.fma} @tab @samp{.movbe}
-@item @samp{.ept} @tab @samp{.clflush} @tab @samp{.lwp}
+@item @samp{.ept} @tab @samp{.clflush}
 @item @samp{.3dnow} @tab @samp{.3dnowa} @tab @samp{.sse4a} @tab @samp{.sse5}
 @item @samp{.syscall} @tab @samp{.rdtscp} @tab @samp{.svme} @tab @samp{.abm}
+@item @samp{.lwp}
 @item @samp{.padlock}
 @end multitable