support for dcbzl instruction for g5/g4/power4?

[Chris Friesen]

The ppc970 chip has a new instruction, "dcbzl".

Apple has stated that the instruction is treated as "dcbz" on the g4, 
and IBM has stated that the instruction is treated as "dcbz" on the 
POWER chips.

On the ppc970, the dcbz instruction has two modes, one for backwards 
compatibility where it zeros out 32 bytes, and one for performance where 
it zeros out 128 bytes and avoids a memory read.

The dcbzl instruction always zeros out a native cacheline.  On the 970 
this is 128 bytes.

The actual instruction is the same as dcbz, but with the 10th bit (in 
IBM's nomenclature where the high order bit is bit zero) set.

ie:

dcbz  0x7c0007ec
dcbzi 0x7c2007ec


Any idea when this will be supported?

Chris